View DS1886T_8522911.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds1886 sfp and pon onu controller with digital ldd interface general description the ds1886 controls and monitors all functions for sff, sfp, and sfp+ modules including all sff-8472 func - tionality for gpon/epon and 10g pon onu applica - tions. the combination of the ds1886 with the max3710 supports all transmitter and receiver functionality. the ds1886 includes modulation current control and apc set- point control with tracking error adjustment. it continually monitors rssi for los generation. a 13-bit analog-to- digital converter (adc) monitors v cc , temperature, laser bias, laser modulation, and receive power to meet all monitoring requirements. receive power measurement is differential with support for common mode to v cc . a 9-bit digital-to-analog converter (dac) is included with temperature compensation for apd bias control. applications sff, sfp, and pon onu modules features s meets all sff-8472 control and monitoring requirements s companion controller for the max3710 laser driver/limiting amplifier and max3945 limiting amplifier s max3710/ds1886 combination supports broad spectrum of continuous mode and pon applications up to 2.5ghz s temperature lookup table (lut) to compensate for apc tracking error and dual closed-loop variables s three laser control modes ? dual closed loop: laser bias and laser modulation are automatically controlled with multiple luts to compensate dual closed-loop calibration points ? apc loop: laser bias automatically controlled, laser modulation controlled by temperature lut ? open loop: laser bias and laser modulation are controlled by temperature luts s 13-bit adc ? laser bias, laser power, and receive power support internal and external calibration ? differential receive power input ? scalable dynamic range ? internal direct-to-digital temperature sensor ? alarm and warning flags for all monitored channels s 10-bit dac with temperature compensation for apd bias s digital i/o pins: transmit disable input/output, rate select input, los input/output, transmit fault input/output, and in1 status monitor and fault input s comprehensive fault measurement system with maskable alarm/warnings s flexible password scheme provides three levels of security s 256-byte a0h and 128-byte upper a2h eeprom s i 2 c-compatible interface s 3-wire master to communicate with the max3710/max3711 laser driver/limiting amplifier and max3945 limiting amplifier 19-6259; rev 1; 8/12 ordering information appears at end of data sheet. for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrated?s website at www.maximintegrated.com. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 2 maxim integrated table of contents general description ............................................................................ 1 applications .................................................................................. 1 features ..................................................................................... 1 absolute maximum ratings ..................................................................... 10 recommended operating conditions ............................................................. 10 dc electrical characteristics .................................................................... 10 dac electrical characteristics ................................................................... 11 analog voltage monitoring characteristics ......................................................... 11 digital thermometer characteristics .............................................................. 11 ac electrical characteristics .................................................................... 12 startup timing characteristics ................................................................... 12 3-wire digital interface specification .............................................................. 12 i 2 c ac electrical characteristics ................................................................. 13 nonvolatile memory characteristics ............................................................... 13 typical operating characteristics ................................................................ 14 pin configuration ............................................................................. 15 pin description ............................................................................... 15 block diagram ............................................................................... 16 typical operating circuit?gpon onu ............................................................ 17 typical operating circuit?10g pon onu ......................................................... 18 detailed description ........................................................................... 19 monitors and fault detection .................................................................. 19 monitors ................................................................................ 19 adc monitors and alarms .................................................................. 20 alarms and warnings ...................................................................... 20 adc timing ............................................................................. 20 right-shifting adc result .................................................................. 21 differential rssi input ..................................................................... 21 laser bias and laser power through txmon .................................................. 22 enhanced rssi monitoring (dual range functionality) ........................................... 22 apd mode ............................................................................. 22 pin mode .............................................................................. 23 low-voltage operation ....................................................................... 23 power-on analog (poa) ...................................................................... 24 delta-sigma output and reference ............................................................. 25 digital i/o pins .............................................................................. 26 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 3 maxim integrated los, losout ........................................................................... 26 rsel .................................................................................. 26 txd, txdout ........................................................................... 26 in1, txf, transmit fault (txfout) output ..................................................... 26 die identification ............................................................................ 27 ds1886 master communication interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3-wire master interface ....................................................................... 28 protocol ................................................................................ 28 3-wire slave register map and ds1886 corresponding location ................................... 29 3-wire master flowchart ................................................................... 29 3-wire power-on reset ....................................................................... 31 ds1886 with max3710 operating modes ........................................................ 32 open loop mode, dpc_en = 0, apc_en = 0 .................................................. 32 apc loop mode, dpc_en = 0, apc_en = 1 ................................................... 32 dual closed-loop mode, dpc_en = 1, apc_en = 1 ............................................ 32 bias, modulation, set_2xapc, txctrl5 luts ................................................ 33 modulation value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 bias value .............................................................................. 34 power leveling ............................................................................. 35 manual max3710 operations .................................................................. 35 i 2 c communication ........................................................................... 35 i 2 c definition ............................................................................... 35 i 2 c protocol ................................................................................ 37 memory organization .......................................................................... 38 register descriptions .......................................................................... 40 a2h lower memory register map .............................................................. 40 a2h table 01h register map ................................................................... 40 a2h table 02h register map .................................................................. 41 a2h table 04h register map .................................................................. 42 a2h table 05h register map .................................................................. 42 a2h table 06h register map .................................................................. 42 a2h table 08h register map .................................................................. 43 a2h table 09h register map .................................................................. 43 auxiliary a0h memory register map ............................................................ 43 a2h lower memory register descriptions ........................................................ 44 a2h lower memory, register 00h?01h: temp alarm hi ........................................ 44 table of contents ( continued) downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 4 maxim integrated a2h lower memory, register 04h?05h: temp warn hi ......................................... 44 a2h lower memory, register 02h?03h: temp alarm lo ........................................ 44 a2h lower memory, register 06h?07h: temp warn lo ......................................... 44 a2h lower memory, register 08h?09h: v cc alarm hi ......................................... 45 a2h lower memory, register 0ch?0dh: v cc warn hi .......................................... 45 a2h lower memory, register 10h?11h: txb alarm hi .......................................... 45 a2h lower memory, register 14h?15h: txb warn hi ........................................... 45 a2h lower memory, register 18h?19h: txp alarm hi .......................................... 45 a2h lower memory, register 1ch?1dh: txp warn hi .......................................... 45 a2h lower memory, register 20h?21h: rssi alarm hi ......................................... 45 a2h lower memory, register 24h?25h: rssi warn hi .......................................... 45 a2h lower memory, register 0ah?0bh: v cc alarm lo ......................................... 46 a2h lower memory, register 0eh?0fh: v cc warn lo .......................................... 46 a2h lower memory, register 12h?13h: txb alarm lo ......................................... 46 a2h lower memory, register 16h?17h: txb warn lo .......................................... 46 a2h lower memory, register 1ah?1bh: txp alarm lo ......................................... 46 a2h lower memory, register 1eh?1fh: txp warn lo .......................................... 46 a2h lower memory, register 22h?23h: rssi alarm lo ........................................ 46 a2h lower memory, register 26h?27h: rssi warn lo ......................................... 46 a2h lower memory, register 28h?37h: empty ................................................ 47 a2h lower memory, register 38h?5fh: ee .................................................... 47 a2h lower memory, register 60h?61h: temp value ........................................... 47 a2h lower memory, register 62h?63h: v cc value ............................................ 48 a2h lower memory, register 64h?65h: txb value ............................................ 48 a2h lower memory, register 66h?67h: txp value ............................................. 48 a2h lower memory, register 68h?69h: rssi value ............................................ 48 a2h lower memory, register 6ah?6dh: reserved ............................................ 48 a2h lower memory, register 6eh: status .................................................... 49 a2h lower memory, register 6fh: update ................................................... 50 a2h lower memory, register 70h: alarm 3 ......................................................... 51 a2h lower memory, register 71h: alarm 2 ......................................................... 52 a2h lower memory, register 72h?73h: reserved ............................................. 52 a2h lower memory, register 74h: warn 3 .......................................................... 53 a2h lower memory, register 75h: warn 2 .......................................................... 54 a2h lower memory, register 76h?7ah: reserved ............................................. 54 table of contents ( continued) downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 5 maxim integrated table of contents ( continued) a2h lower memory, register 7bh?7eh: password entry (pwe) ................................ 55 a2h lower memory, register 7fh: tbl sel ................................................... 55 a2h table 01h register descriptions ............................................................ 56 a2h table 01h, register 80h?bfh: eeprom ................................................... 56 a2h table 01h, register c0h?f7h: eeprom .................................................. 56 a2h table 01h, register f8h: alarm en 3 ........................................................... 57 a2h table 01h, register f9h: alarm en 2 .......................................................... 58 a2h table 01h, register fah?fbh: reserved ................................................. 58 a2h table 01h, register fch: warn en 3 ........................................................... 59 a2h table 01h, register fdh: warn en 2 ........................................................... 60 a2h table 01h, register feh?ffh: reserved or ee ........................................... 60 a2h table 02h register descriptions ............................................................ 61 a2h table 02h, register 80h: mode ......................................................... 61 a2h table 02h, register 81h: temperature index (tindex) ....................................... 62 a2h table 02h, register 82h ? 83h: modulation value ........................................ 62 a2h table 02h, register 84h: reserved ..................................................... 62 a2h table 02h, register 85h: apc value .................................................... 63 a2h table 02h, register 86h ? 87h: set_ibias value ........................................... 63 a2h table 02h, register 88h: dacfs ........................................................ 63 a2h table 02h, register 89h: cnfga ........................................................ 64 a2h table 02h, register 8ah: cnfgb ........................................................ 65 a2h table 02h, register 8bh: cnfgc ........................................................ 66 a2h table 02h, register 8ch: reserved .................................................... 66 a2h table 02h, register 8dh: cnfgd ....................................................... 67 a2h table 02h, register 8eh: right-shift 1 (rshift 1 ) .......................................... 67 a2h table 02h, register 8fh: right-shift 0 (rshift 0 ) .......................................... 68 a2h table 02h, register 90h?91h: xover coarse ............................................ 68 a2h table 02h, register 92h ? 93h: v cc scale ................................................ 69 a2h table 02h, register 94h ? 95h: txb scale ................................................ 69 a2h table 02h, register 96h ? 97h: txp scale ................................................. 69 a2h table 02h, register 98h?99h: rssi fine scale ........................................... 69 a2h table 02h, register 9ah?9bh: reserved ................................................ 69 a2h table 02h, register 9ch?9dh: rssi coarse scale ....................................... 69 a2h table 02h, register 9eh ? 9fh: reserved ................................................. 69 a2h table 02h, register a0h?a1h: xover fine ................................................ 70 a2h table 02h, register a2h?a3h: v cc offset ............................................... 70 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 6 maxim integrated table of contents ( continued) a2h table 02h, register a4h?a5h: txb offset ............................................... 70 a2h table 02h, register a6h?a7h: txp offset ............................................... 70 a2h table 02h, register a8h?a9h: rssi fine offset .......................................... 70 a2h table 02h, register aah?abh: reserved ................................................ 70 a2h table 02h, register ach?adh: rssi coarse offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 a2h table 02h, register aeh?afh: internal temp offset .................................... 71 a2h table 02h, register b0h ? b3h: pw1 ...................................................... 71 a2h table 02h, register b4h ? b7h: pw2 ...................................................... 72 a2h table 02h, register b8h?bfh: empty .................................................... 72 a2h table 02h, register c0h: pw_ena ....................................................... 73 a2h table 02h, register c1h: pw_enb ....................................................... 74 a2h table 02h, register c2h ? c6h: reserved ................................................ 75 a2h table 02h, register c7h: tblselpon .................................................... 75 a2h table 02h, register c8h ? c9h: dac value ................................................ 75 a2h table 02h, register cah: incbyte ...................................................... 76 a2h table 02h, register cbh: txctrl5 dpc .................................................. 76 a2h table 02h, register cch: imodmax ..................................................... 76 a2h table 02h, register cdh: ibiasmax ..................................................... 77 a2h table 02h, register ceh: device id ..................................................... 77 a2h table 02h, register cfh: device ver ................................................... 77 a2h table 02h, register d0h ? dfh: empty ................................................... 78 a2h table 02h, register e0h: rxctrl1 ...................................................... 78 a2h table 02h, register e1h: rxctrl2 ...................................................... 78 a2h table 02h, register e2h: setcml ....................................................... 79 a2h table 02h, register e3h: setlosh ...................................................... 79 a2h table 02h, register e4h: txctrl1 ....................................................... 79 a2h table 02h, register e5h: txctrl2 ...................................................... 80 a2h table 02h, register e6h: txctrl3 ...................................................... 80 a2h table 02h, register e7h: txctrl4 ...................................................... 80 a2h table 02h, register e8h: txctrl5 apc ol ............................................... 81 a2h table 02h, register e9h: txctrl6 ...................................................... 81 a2h table 02h, register eah: txctrl7 ...................................................... 81 a2h table 02h, register ebh: reserved ..................................................... 82 a2h table 02h, register ech: setlosh_3945 ................................................. 82 a2h table 02h, register edh: setlosl_3945 ................................................. 82 a2h table 02h, register eeh: setlostimer_3945 ............................................. 83 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 7 maxim integrated table of contents ( continued) a2h table 02h, register efh: 3wset ........................................................ 83 a2h table 02h, register f0h: 3wctrl ....................................................... 84 a2h table 02h, register f1h: address ...................................................... 84 a2h table 02h, register f2h: write ......................................................... 85 a2h table 02h, register f3h: read ......................................................... 85 a2h table 02h, register f4h: t xstat2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 a2h table 02h, register f5h: txstat1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 a2h table 02h, register f6h: dpcstat ...................................................... 86 a2h table 02h, register f7h: rxstat ........................................................ 86 a2h table 02h, register f8h?ffh: reserved ................................................. 86 a2h table 04h register descriptions ............................................................ 87 a2h table 04h, register 80h?a7h: modulation or txctrl5 lut ................................ 87 a2h table 04h, register a8h?efh: empty .................................................... 87 a2h table 04h, register f0h?f7h: mod max lut ............................................. 87 a2h table 04h, register f8h?ffh: mod offset or set_imod lut ............................... 88 a2h table 06h register descriptions ............................................................ 88 a2h table 06h, register 80h?a7h: bias or set_ibias .......................................... 88 a2h table 06h, register a8h?efh: empty .................................................... 89 a2h table 06h, register f0h?f7h: bias max lut .............................................. 89 a2h table 06h, register f8h?ffh: bias offset or apc lut ..................................... 89 a2h table 08h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 a2h table 08h, register 80h ? f7h: empty .................................................... 90 a2h table 08h, register f8h ? ffh: incbyte .................................................. 90 a2h table 09h register descriptions ............................................................ 90 a2h table 09h, register 80h ? f7h: empty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 a2h table 09h, register f8h ? ffh: dac offset lut ........................................... 90 auxiliary memory a0h register description ....................................................... 91 auxiliary memory a0h, register 00h?ffh: eeprom ............................................. 91 applications information ........................................................................ 91 power-supply decoupling ..................................................................... 91 layout considerations ........................................................................ 91 sda and scl pullup resistors ................................................................. 91 ordering information .......................................................................... 91 package information ........................................................................... 91 revision history .............................................................................. 92 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 8 maxim integrated figure 1a. adc channel only for txp when burst_mode = 1 in table 02h, register 89 h .................. 19 figure 1b. adc channel ....................................................................... 19 figure 2. adc round-robin timing ............................................................... 21 figure 3. rssi differential input for high-side rssi .................................................. 21 figure 4. laser bias (txb) and laser power (txp) monitoring through tx mon ........................... 22 figure 5. rssi in apd mode .................................................................... 22 figure 6. rssi in pin mode ..................................................................... 23 figure 7. low-voltage hysteresis example ......................................................... 24 figure 9. delta-sigma output ................................................................... 25 figure 8. recommended shunt reference and rc filter for dac output ................................. 25 figure 10. txfout and txdout logic diagram. ................................................... 26 figure 11. rsel logic diagram .................................................................. 26 figure 12a. txfout nonlatched operation ........................................................ 27 figure 12b. txfout latched ................................................................... 27 figure 12c. txfout during power-on ............................................................ 27 figure 13. 3-wire interface timing diagram ........................................................ 28 figure 14. 3-wire flowchart ..................................................................... 30 figure 15. max3710 brownout detection flowchart .................................................. 31 figure 16. offset lut .......................................................................... 34 figure 17. modulation lut (open loop and apc mode) ........................................... 34 figure 18. bias lut (open loop) ................................................................ 34 figure 19. i 2 c timing diagram .................................................................. 36 figure 20. example i 2 c timing .................................................................. 37 figure 21. memory organization ................................................................. 39 list of figures downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 9 maxim integrated list of tables table 1. acronyms ............................................................................ 19 table 2. adc default monitor full-scale ranges .................................................... 20 table 3. rssi hysteresis threshold values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 4. rssi configuration registers ............................................................. 23 table 5. 3-wire transaction detail ................................................................ 28 table 6. 3-wire register map and ds1886 corresponding location ..................................... 29 table 7. ds1886 lut functions in open loop, apc loop, and dual closed- loop modes .................... 32 table 8. ds1886 lut memory map for 5-row table (temperature values indica ted in c) ........................ 33 table 9. ds1886 lut memory map for 5-row table (tindex values indicate d in hex) ...................... 33 table 10. temperature resolution for offsets ....................................................... 34 table 11a. power leveling details (when ds1863_mode = 0, default) ................................... 35 table 11b. power leveling details (when ds1863_mode = 1) .......................................... 35 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 10 maxim integrated (all voltages relative to ground.)voltage range on in1, dac, los, rssip, rssin, refin, rsel, txf, txmon, txd ......... -0.5v to (v cc + 0.5v) (subject to not exceeding +6v) voltage range on v cc , sda, scl, txfout and losout ....................................................... -0.5v to +6v continuous power dissipation (t a = +70 n c) tqfn (derate 28.6mw/ n c above +70 n c) ............... 2285.7mw operating temperature range .......................... -40 n c to +95 n c programming temperature range ....................... 0 n c to +95 n c storage temperature range ............................ -55 n c to +125 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratingsstresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions (t a = -40 n c to +95 n c, unless otherwise noted.) (note 1) dc electrical characteristics(v cc = +2.97v to +3.63v, t a = -40 n c to +95 n c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units main supply voltage v cc (note 2) 2.97 3.63 v high-level input voltage(sda, scl, sdaout) v ih:1 0.7 x v cc v cc + 0.3 v low-level input voltage(sda, scl, sdaout) v il:1 -0.3 +0.3 x v cc v high-level input voltage(in1, los, rsel, txd, txf) v ih:2 2.0 v cc + 0.3 v low-level input voltage(in1, los, rsel, txd, txf) v il:2 -0.3 +0.8 v parameter symbol conditions min typ max units supply current i cc (notes 2, 3) 0.7 2 ma output leakage(losout, sda, sdaout, txfout) i lo 1 f a low-level output voltage(csel1out, csel2out, losout, sda, sdaout, sclout, txdout, txfout) v ol i ol = 4ma 0.4 v i ol = 6ma 0.6 high-level output voltage (csel1out, csel2out, sclout, sdaout, txdout) v oh i oh = 4ma v cc - 0.4 v input leakage current(in1, los, rsel, scl, txd, txf) i li 1 f a digital power-on reset pod 1.6 2.6 v analog power-on reset poa poa > pod by design 2.2 2.8 v downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 11 maxim integrated dac electrical characteristics(v cc = +2.97v to +3.63v, t a = -40 n c to +95 n c, unless otherwise noted.) (note 1) analog voltage monitoring characteristics(v cc = +2.97v to +3.63v, t a = -40 n c to +95 n c, unless otherwise noted.) (note 1) digital thermometer characteristics(v cc = +2.97v to +3.63v, t a = -40 n c to +95 n c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units delta-sigma input clock frequency f ds 2.1 mhz reference voltage input (refin) v refin minimum 0.1f to gnd 2 v cc v output range 0 v refin v output resolution see the delta-sigma output and reference section for details (dac fs[9:2] = ffh) 10 bits output impedance r ds v refin = 2.5v 45 100 i recovery after power-up t init_dac from v cc > vcc lo alarm or warning see the startup timing characteristics table ms parameter symbol conditions min typ max units adc resolution (note 4) 13 bits inl t a = +25 n c -3 +3 lsb dnl -1 +1 lsb update rate for temperature, txmon (txb/txp), rssip-rssin, v cc t rr rssip-rssin requires only a coarse conversion (note 5) 30 ms update rate for rssip-rssin t r/r2 rssip-rssin requires a fine conversion 36 ms input/supply offset (txmon, rssip, rssin, v cc ) v os (notes 5, 6) -1 0 +1 lsb factory setting full scale txmon and rssip-rssin coarse (notes 6, 7) 2.5 v v cc (note 7) 6.5536 rssip-rssin fine (note 7) 312.5 v temperature lsb weighting 1/256 n c parameter symbol conditions min typ max units thermometer error t err -40 n c to +95 n c, guaranteed by design -3 +3 n c downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 12 maxim integrated ac electrical characteristics(v cc = +2.97v to +3.63v, t a = -40 n c to +95 n c, unless otherwise noted.) (note 1) startup timing characteristics(v cc = +2.97v to +3.63v, t a = -40 n c to +95 n c, unless otherwise noted.) (note 1) 3-wire digital interface specification(v cc = +2.97v to +3.63v, t a = -40 n c to +95 n c, unless otherwise noted. timing is referenced to v il(max) and v ih(min) .) (note 1) (see figure 13 .) parameter symbol conditions min typ max units txd rising edge to fault clear t off from h txd (notes 8, 9) 5 f s txd falling edge to txdout falling t on from i txd (note 10) 5 f s recovery after power-up:max3710 t init_3710 from h v cc > poa (note 11) 1 ms recovery after power-up:max3710 and max3945 t init_3945 from h v cc > vcc lo alarm or warning (note 12) 1 ms fault assert time(to txfout = 1) t initr1 from i txd 30 ms fault reset time at power-on(to txfout = 0) t initr2 from h v cc > poa, figure 12c (note 13) 12.5 ms parameter symbol conditions min typ max units output enable time following poa t init (notes 13, 14) 13 ms parameter symbol conditions min typ max units sclout clock frequency f sclout 1.05 mhz sclout duty cycle t 3wdc 50 % sdaout setup time t ds 500 ns sdaout hold time t dh 100 ns csel1out, csel2out pulse-width low t csw 1 f s csel1out, csel2out leading time before the first sclout edge t l 1 f s csel1out, csel2out trailing time after the last sclout edge t t 1 f s sdaout, sclout load c b3w total bus capacitance on one line 10 pf downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 13 maxim integrated i 2 c ac electrical characteristics (v cc = +2.97v to +3.63v, t a = -40 n c to +95 n c, unless otherwise noted. timing is referenced to v il(max) and v ih(min) .) (note 1) (see figure 19 .) nonvolatile memory characteristics(v cc = +2.97v to +3.63v, unless otherwise noted.) (note 1) note 1: limits are production tested at t a = +25c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. typical values are not guaranteed. note 2: all voltages are referenced to ground. current entering the ic is considered positive, and current exiting the ic is consid - ered negative. note 3: inputs are at supply rail. outputs are not loaded. does not include refin current. measured using the typical operating circuit?gpon onu . note 4: the adc output is available internally as a 16-bit value. the 16 bits are derived by left-shifting the 13-bit adc output by 3. note 5: guaranteed by design. note 6: txb (transmit bias) and txp (transmit power) are separate adc conversions that are performed on the same input pin, txmon. note 7: full scale is user-programmable. note 8: time until faults are cleared (falling edge of txfout). note 9: time until rising edge of txdout. note 10: time until falling edge of txdout. note 11: time until completion of initial max3710 control registers configuration. note 12: time until completion of initial max3945 and max3710 control registers configuration. note 13: vcc lo alarm or warning is enabled, a v cc conversion is completed, and v cc is above vcc lo alarm or warning. see figure 12c . note 14: dac output valid, 3-wire writes from luts complete, and digital outputs valid. note 15: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c stan - dard mode. note 16: c b = total capacitance of one bus line in pf. note 17: eeprom write begins after a stop condition occurs. parameter symbol conditions min typ max units scl clock frequency f scl (note 15) 0 400 khz clock pulse-width low t low 1.3 f s clock pulse-width high t high 0.6 f s bus free time between stop and start condition t buf 1.3 f s start hold time t hd:sta 0.6 f s start setup time t su:sta 0.6 f s data in hold time t hd:dat 0 0.9 f s data in setup time t su:dat 100 ns rise time of both sda and scl signals t r (note 16) 20 + 0.1c b 300 ns fall time of both sda and scl signals t f (note 16) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 f s capacitive load for each bus line c b 400 pf eeprom write time t w (note 17) 20 ms parameter symbol conditions min typ max units eeprom write cycles at t a = +25 n c 50,000 ? at t a = +85 n c 10,000 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 14 maxim integrated typical operating characteristics (t a = +25c, unless otherwise noted.) supply current vs. supply voltage ds1886 toc01 v cc (v) supply current (ma) 3.85 3.60 3.35 3.10 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.800.30 2.85 sda = scl = v cc -40c +25c +95c txmon and rssi inl ds1886 toc03 txmon and rssi input voltage (v) txmon and rssi inl (lsb) 2.0 1.5 1.0 0.5 -2 -1 0 1 2 3 -3 0 2.5 using factory-programmed full-scale value of 2.5v v cc = 3.3v dac inl ds1886 toc05 dac position (dec) dac inl (lsb) 500 400 100 200 300 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 0 supply current vs. temperature ds1886 toc02 temperature (c) supply current (ma) 60 10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 -40 sda = scl = v cc v cc = 2.85v v cc = 3.3v v cc = 3.9v txmon and rssi dnl ds1886 toc04 txmon and rssi input voltage (v) txmon and rssi dnl (lsb) 2.0 1.5 1.0 0.5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 2.5 using-factory programmed full-scale value of 2.5v v cc = 3.3v dac dnl ds1886 toc06 dac position (dec) dac dnl (lsb) 500 400 300 200 100 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 15 maxim integrated pin configuration pin description pin name function 1 csel2out chip-select output. part of the 3-wire interface to the max3945. 2 scl i 2 c serial-clock input 3 sda open-drain i 2 c serial-data input/ output 4 txfout open-drain transmit fault output 5 los loss-of-signal input 6 in1 digital maskable fault input 7 txd transmit disable input 8, 15, 17 gnd ground 9 rsel rate select input 10 txdout transmit disable output 11, 12 rssip, rssin differential external monitor input 13 txmon external monitor input for both transmit power (txp) and transmit bias (txb) 14, 16 v cc power-supply input 18 dac dac output 19 refin reference input for dac full scale 20 csel1out chip-select output. part of the 3-wire interface to the max3710. 21 sclout serial-clock output. part of the 3-wire interface to the max3710. 22 sdaout serial-data input/output. part of the 3-wire interface to the max3710. 23 losout open-drain receive loss-of-signal output 24 txf transmit fault input ? ep exposed pad. connect to ground. tqfn (4mm 5mm 0.75mm) top view ds1886 1 csel2out 2 scl 3 sda 4 txfout 5 los 6 in1 7 txd ep 19 refin 18 dac 17 gnd 16 v cc 15 gnd txf losout sdaout sclout csel1out 14 v cc 13 txmon 8 gnd 9 rsel 10 txdout 11 rssip 12 rssin 24 23 22 21 20 + downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 16 maxim integrated block diagram analog mux a2h memory eeprom/sram adc configuration/results, system status/control bits, alarms/warnings, lookup tables, user memory i 2 c interface 3-wire master temperature sensor configurable logic poa and pod reset calculated txp eeprom 256 bytes at a0h sda scl v cc v cc txmon txb mon_sel txp rssip rssin configurable logic 10-bit delta-sigma 13-bit adc dac sdaout sclout csel1out csel2outtxfout refintxdout losout txd txf in1 rsel los gnd ds1886 v cc * see figure 1a , 1b downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 17 maxim integrated typical operating circuit?gpon onu los txfout benp/n txdout refin txd fault disable rsel los losout txf in1 tx_fault sda scl mode_def2 (sda)rate select los mode_def1 (scl) tx_disable lpd laser signal detect mod dac bias dac eeprom 2.5v ref current monitor dac dc-dc control adc i 2 c 3w dc-dc output 3w ds1886 max3710 ds3920 txmonrssip bmon mdin rssin los dac la apd-tia md and dfb ldd downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 18 maxim integrated typical operating circuit?10g pon onu los txfout benp/n txdout refin txd fault disable rsel los losout txf in1 tx_fault sda scl mode_def2 (sda)rate select los mode_def1 (scl) tx_disable lpd laser signal detect mod dac bias dac eeprom 2.5v ref dc-dc control adc i 2 c 3w 3w ds1886 max3710 max3945 3w txmonrssip bmon mdin 10g la 10g apd-tia md and dfb ldd dac current monitor dc-dc output ds3920 rssin 1.25g to 2.5g tosa downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 19 maxim integrated detailed description the ds1886 integrates the control and monitoring func - tionality required to implement an sfp or pon onu system using the maxim max3710 or other compatible laser driver and limiting amplifier. key components of the ds1886 are shown in the block diagram and described in subsequent sections. monitors and fault detection monitors the ds1886 monitors five adc channels. this monitoring combined with the alarm enables (a2h table 01h/05h) determines when/if the ds1886 turns off the max3710 dacs and triggers the txfout and txdout outputs. all the monitoring levels and interrupt masks are user- programmable. see figure 1a . table 1. acronymsfigure 1a. adc channel only for txp when burst_mode = 1 in table 02h, register 89h figure 1b. adc channel acronym description adc analog-to-digital converter apc automatic power control apd avalanche photodiode dac digital-to-analog converter los loss of signal lut lut nv nonvolatile qt quick trip rosa receiver optical subassembly see shadowed eeprom acronym description sff small form factor sff-8472 document defining register map of sfps and sffs sfp small form-factor pluggable sfp+ enhanced sfp te tracking error. deviation from linear of the relationship between transmitted power and monitor diode current. tia transimpedance amplifier tosa transmit optical subassembly txp transmit power 16 16 offset registers 16 16 right-shift2 determined by krmd compare (md0regh[7:0] + 8 x md1regh[7:0]) 65,536 txp scale txfint shift alarm and warning thresholds results registers alarm/ warning flags alarm/ warning enables coupled* shift right-shift1 determined by kimd (a)* user has to calibrate the gain using the scale registers in case right-shifting is desired in order to maintain correct bit weighting. x txp = adc 13 offset registers scale registers 13 13 right-shift settings compare analog input txfint shift alarm and warning thresholds alarm/ warning flags alarm/ warning enables coupled * * user has to calibrate the gain using the scale registers in case right-shifting is desired in order to maintain correct bit weighting. (b) 13 results registers downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 20 maxim integrated adc monitors and alarms the adc monitors temperature (internal temp sen - sor), v cc , laser bias (txb), laser power (txp), and receive power (rssic for coarse, rssif for fine) using an analog multiplexer to measure them using a round-robin scheme with a single adc (see the adc timing section). the voltage channels have a customer-programmable full-scale range and all chan - nels have a customer-programmable offset value that is factory programmed to a default value ( table 2 ). additionally, txb, txp, rssic, and rssif can right-shift results as described in the right-shifting adc result section. this allows customers with specified adc ranges to calibrate the adc input gain by a factor of 2 n to measure small signals (thereby reducing the full scale by a factor of 2 n ). the ds1886 can then right-shift the results by n bits (effectively multiplying by a factor of 1/2 n ) to maintain the bit weight of their specification. see the right-shifting adc result and enhanced rssi monitoring (dual range functionality) sections for more information. alarms and warnings the adc results (after right-shifting, if used) are compared to the alarm and warning thresholds after each conversion, and the corresponding alarms and/ or warnings are set, which can be programmed to create the internal signal txfint. the status of txfint can be read in a2h lower memory, register 71h . txfint is one of the signals used to trigger txfout. txfout can be programmed to cause txdout outputs. these adc thresholds are user-programmable, as are the masking registers that can be used to prevent the alarms from triggering the txfout and txdout outputs. adc timing five analog channels are digitized in a round-robin fashion in the order as shown in figure 2 . rssi is measured twice to obtain coarse and fine measure - ments (rssic and rssif, respectively). the total time required to convert all channels is t rr (see the analog voltage monitoring characteristics table for details). after each txmon conversion, a 3-wire communication is initiated to toggle the mon_sel bit (bit 6 in the max3710?s txctrl2 register, programmed through a2h table 02h, register e5h , bit 6). this causes the laser driver to alternate sending laser bias (txb) and laser power (txp) signals to the ds1886?s txmon input. the ds1886 has a burst mode option to allow internal calculation of txp using the md0 and md1 register values read from the max3710 over the 3-wire inter - face. in this option, the sampled txp value is ignored. the txp value in this burst mode is calculated as follows: (md0 regh [7:0] + 8 x md1 regh [7:0]) x 65536 txp txp scale = txp is then right-shifted ( figure 1a ). right-shift 1 is determined by kimd[1:0], txctrl3[4:3] as follows: table 2. adc default monitor full-scale ranges signal (units) +fs signal +fs hex -fs signal -fs hex temperature (c) 127.996 7fffh -128 8000h v cc (v) 6.5528 fff8h 0 0000h txb, txp, rssic, rssif (v) 2.4997 fff8h 0 0000h kimd[1:0] txctrl3[4:3] no. of right-shifts 00 2 01 1 10 0 11 0 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 21 maxim integrated figure 2. adc round-robin timing right-shift 2 is determined by krmd[1:0], txctrl3[2:1] as follows: right-shifting adc result the right-shift operation on the adc result is carried out based on the contents of right-shift control registers ( a2h table 02h, register 8eh and a2h table 02h, register 8fh ) in eeprom. txb, txp, rssic, and rssif have 3 bits allocated to set the number of right-shifts. the user must calibrate the corresponding monitors to achieve the correct lsb weighting. up to seven right-shift operations are allowed and are executed as a part of every conver - sion before the results are compared to the high and low alarm levels, or loaded into their corresponding measure - ment registers (lower memory, registers 64h?69h). this is true during the setup of internal calibration as well as during subsequent data conversions. in burst mode, right-shifting for txp is determined by kimd and krmd. differential rssi input the ds1886 offers a fully differential input for rssi that enables high-side monitoring of rssi, as shown in figure 3 . this reduces board complexity by eliminating the need for a high-side differential amplifier or a cur - rent mirror. figure 3. rssi differential input for high-side rssi krmd[1:0] txctrl3[4:3] no. of right-shifts 00 2 01 1 10 0 11 0 temp v cc txb rssic toggle mon_sel rssif txp temp t rr note: if vcc lo alarm or warning is enabled at power-up, the adc round-robin timing cycles between temperature and v cc only until v cc is above the vcc lo alarm threshold. toggle mon_sel rssiprssin adc 680 rosa v cc ds1886 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 22 maxim integrated laser bias and laser power through txmon the ds1886 measures both laser bias (txb) and laser power (txp) through the same input pin, txmon. the ds1886 commands the max3710 laser driver to output the correct monitor signal before each adc conversions takes place. figure 4 shows the two conversion paths. each path has independent gain and offset calibration registers. enhanced rssi monitoring (dual range functionality) the ds1886 offers a feature to improve the accuracy and range of rssi, which is most commonly used for monitoring rssi. to achieve the sff-8472 requirement of 0.1w/lsb over -40 to 8.2dbm, the ds1886 makes two measurements to effectively achieve a 16-bit conversion with a 13-bit physical adc. this ?dual range? calibration can operate in two modes: apd mode and pin mode. apd mode for systems with a nonlinear relationship between the adc input and desired adc result, the mode should be set to apd mode ( figure 5 ). the rssi measurement of an apd receiver is one such application. using the apd mode allows a piece-wise linear approximation of the nonlinear response of the apd?s gain factor. the crossover point is the point between fine and coarse points. the adc result transitions between the fine and coarse ranges with no hysteresis. right-shifting, slope adjustment, and offset are configurable for both the fine and coarse ranges. two registers, xover fine and xover coarse, determine the crossover point. the xover fine register ( a2h table 02h, register a0h?a1h ) determines the maximum results returned by fine adc conversions, before right-shifting. the xover coarse register ( a2h table 02h, register 90h?91h ) determines the minimum results returned by coarse adc conversions, before right-shifting. figure 5. rssi in apd mode figure 4. laser bias (txb) and laser power (txp) monitoring through txmon crossover point rssi result apd mode ideal response fine full-scale response coarse full-scale response rssi input txmon bmonmon_sel = 0 txbtxp adcadc ds1886 max3710 txmon bmonmon_sel = 1 txbtxp adcadc ds1886 max3710 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 23 maxim integrated figure 6. rssi in pin mode pin modethe pin mode is intended for systems with a linear rela - tionship between the rssi input and desired adc result. the adc result transitions between the fine and coarse ranges with hysteresis, as shown in figure 6 . in pin mode, the thresholds between coarse and fine mode are a function of the number of right-shifts being used. with the use of right-shifting, the fine mode full scale is programmed to (1/2 nth ) of the coarse mode full scale. the ds1886 now auto ranges to choose the range that gives the best resolution for the measurement. table 3 shows the threshold values for each possible number of right-shifts. low-voltage operation the ds1886 contains two power-on reset (por) levels. the lower level is a digital por (pod) and the higher level is an analog por (poa). at startup, before the supply voltage rises above poa, the outputs are dis - abled, all sram locations are set to their defaults, shadowed eeprom locations are zero, and all analog table 3. rssi hysteresis threshold values* this is the minimum reported coarse mode conversion. table 4. rssi configuration registers # of right- shifts fine mode max (hex) coarse mode min* (hex) 0 fff8h f000h 1 7ffch 7800h 2 3ffeh 3c00h 3 1fffh 1e00h 4 0fffh 0f00h 5 07ffh 0780h 6 03ffh 03c0h 7 01ffh 01e0h register fine mode coarse mode gain register (rssi fine/coarse scale) 98h?99h, a2h table 02h 9ch?9dh, a2h table 02h offset register (rssi fine/coarse offest) a8h?a9h, a2h table 02h ach?adh, a2h table 02h right-shift 1 register 8eh, a2h table 02h n/a rssic and rssif bits (right-shift 0 ) 8fh, a2h table 02h rssir bit (update) 6fh, a2h lower memory rssi measurement (rssi value) 68h?69h, a2h lower memory pin mode rssi result fine full-scale response coarse full-scale response fine right-shift = 3 rssi input fine coarse hysteresis downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 24 maxim integrated figure 7. low-voltage hysteresis example circuitry is disabled. when v cc reaches poa, the see is recalled, and the analog circuitry is enabled. while v cc remains above poa, the device is in its normal operating state, and it responds based on its nonvolatile configura - tion. if during operation v cc falls below poa, but is still above pod, the sram retains the see settings from the first see recall, but the device analog is shut down and the outputs are disabled. if the supply voltage recovers back above poa, the device immediately resumes nor - mal operation. if the supply voltage falls below pod, the device sram is placed in its default state and another see recall is required to reload the nonvolatile settings. the eeprom recall occurs the next time v cc next exceeds poa. figure 7 shows the sequence of events as the voltage varies.any time v cc is above pod, the i 2 c interface can be used to determine if v cc is below the poa level. this is accomplished by checking the rdyb bit in the status byte ( a2h lower memory, register 6eh ). rdyb is set when v cc is below poa; when v cc rises above poa, rdyb is timed (within 500 f s) to go to 0, at which point the part is fully functional.for all device addresses sourced from eeprom ( a2h table 02h, register 8ch ), the default device address is a2h until v cc exceeds poa, allowing the device address to be recalled from the eeprom. power-on analog (poa) poa holds the ds1886 in reset until v cc is at a suitable level (v cc > poa) for the device to accurately measure with its adc and compare analog signals with its quick-trip monitors. because v cc cannot be measured by the adc when v cc is less than poa, poa also asserts the vcc lo alarm, which is cleared by a v cc adc conver - sion greater than the customer-programmable v cc low adc limit. this allows a programmable limit to ensure that the head room requirements of the transceiver are satisfied during a slow power-up. the txfout output does not latch until there is a conversion above the v cc low limit. the poa alarm is nonmaskable. see the low- voltage operation section for more information. v poa v pod v cc see recalled value recalled value precharged to 0 precharged to 0 precharged to 0 see recall see recall downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 25 maxim integrated figure 8. recommended shunt reference and rc filter for dac output delta-sigma output and reference one delta-sigma output (dac) is provided. this provides a 10-bit resolution output. the maximum voltage output is set by the input refin. an inexpensive shunt reference is recommended to generate the voltage applied to refin, as shown in figure 8 . the output includes the ability to compensate the apd bias for temperature as given by the following formula: dac_int = tindex[6:0] + dac offset if inv_dac = 0, then dac[9:0] = dac_int/dacfs x v refin . if inv_dac = 1, then dac[9:0] = [3ff - (dac_int/dacfs)] x v refin . where: 1) inv_dac is at a2h table 02h, register 8dh , bit 7. 2) tindex is at a2h table 02h, register 81h . 3) dac offset is an 8-bit value, representing the 8 msbs of a 10-bit value. the two lsbs are 0. 4) dacfs ( a2h table 02h, register 88h ) is an 8-bit value, representing the 8 msbs of a 10-bit value. the two lsbs are 0. 5) dac is a 10-bit value. 6) the dac[9:0] is clamped at dacfs. 7) dac_int is an internal signal. the delta-sigma output uses pulse-density modulation. it provides much lower output ripple than a standard digital pwm output given the same clock rate and filter components. an rc filter is required on the dac output as suggested in figure 8 . the external rc filter compo - nents are chosen based on ripple requirements, output load, delta sigma frequency, and desired response time. before t init , the dac output is high impedance. the reference input, refin, is the supply voltage for the dac?s output buffer. the voltage source connected to refin must be able to support the edge rate require - ments of the delta sigma outputs. in a typical application, a 0.1uf capacitor should be connected between refin and ground. the ds1886?s delta-sigma output is 10 bits. for illustra - tive purposes, a 3-bit example is provided in figure 9 . figure 9. delta-sigma output o 12 3 4 5 6 7 ds1886 refin 2.5v 0.1f0201 ztl431asot23 1f0402 connect tocontrol input on dc-dc 39.2k 0201 dac 68.1k 0201 1k 0201 20k 0201 v cc downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 26 maxim integrated digital i/o pins five digital inputs and three digital output pins are pro - vided for monitoring and control. los, losout by default, the los pin is used to convert a standard comparator output for loss of signal (los) to an open- collector output (losout). the status of los can be read in the status byte ( a2h lower memory, register 6eh ) as the rxl bit. the rxl signal can be inverted (inv los = 1) before driving the open drain output transistor. rsel the level of rsel can be read by reading the status register ( a2h lower memory, register 6eh ). the status of rsel determines whether setlosl or setlosh is written to the max3945 register set_los. txd, txdout txdout is generated from a combination of txfout and txd (see the cnfgc register a2h table 02h, register 8bh for enabling these options). a software control identical to txd is available (txdc, a2h lower memory, register 6eh ). a txd pulse is internally extend - ed (t initr1 ) to inhibit the latching of low alarms and warnings. the intended use is a direct connection to the max3710?s disable input if this is desired. when v cc < poa, txdout is high impedance. in1, txf, transmit fault (txfout) output txfout can be triggered by all alarms and warnings and also the pins txf and in1 ( figure 10 ). the adc alarms and warnings require enabling (a2h table 01h/05h, registers figure 10. txfout and txdout logic diagram.figure 11. rsel logic diagram cc d q q r out in txds r pu txfs txfouts txd txfint t initr1 txdc v cc txd txdout txdio txdflt fault reset timer (130ms) in out power-on reset pins invtxf txf txfout in1s in1en in1 rsel rsels 3-wireset_los_3945 = pins downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 27 maxim integrated f8h and fdh). see figure 12a and figure 12b for non - latched and latched operation. figure 12c describes this txfout behavior during power-on. latching of the alarms is controlled by cnfgb and cnfgc registers ( a2h table 02h, register 8ah and a2h table 02h, register 8bh ). the ds1886 monitors the imodovfl and ibiasovfl bits in the max3710 dpcstat register. if any of these bits is set, the user can optionally cause txfout to be set. a mask bit, biasmodovfl_flt in a2h table 02h, register 8bh , must be set to enable this functionality. die identification the ds1886 has an id hardcoded in its die. two registers (device id a2h table 02h, register ceh and device ver a2h table 02h, register cfh ) are assigned for this feature. register ceh reads 84h to identify with the device as the ds186, and register cfh reads the present device version. figure 12a. txfout nonlatched operationfigure 12b. txfout latched figure 12c. txfout during power-on txfout detection of txfout fault txfout detection of txfout fault txd or txf reset v poa v cc txfout 1 txfout 2 condition 1: vcc lo alarm or warning flag enabled to create txf. v cc is above corresponding vcc lo alarm/warning threshold. condition 2: vcc lo alarm and warning flags are not enabled. t initr2 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 28 maxim integrated ds1886 master communication interface the ds1886 controls the max3710 using a proprietary 3-wire interface. the ds1886 configures the max3710 on startup and then continuously updates the max3710 with new lut values. the ds1886 operates in one of three modes: open loop, apc loop, and dual closed loop. the ds1886 can also configure the max3945 on startup. the communication between the ds1886 and the max3710 and max3945 is transparent to the end user. in addition, commands can be issued to the max3710 and max3945 using the ds1886?s manual mode. 3-wire master interface the ds1886 acts as the master, initiating communica - tion with and generating the clock for the maxim slave device(s). it is a 3-pin interface consisting of sdaout, a bidirectional data line; clock signal sclout; and csel1out chip-select output (active high). a second, independent chip select (csel2out) is provided for use with the max3945. protocol the ds1886 initiates a data transfer by asserting the csel1out or csel2out pin. it then starts to generate a clock signal after csel1out or csel2out has been set to 1. each operation consists of 16 bit transfers (15-bit address/data, 1-bit rwn). all data transfers are msb first. write mode (rwn = 0): the master generates 16 clock cycles at sclout in total. it outputs 16 bits (msb first) to the sdaout line at the falling edge of the clock. the master closes the transmission by setting csel1out and csel2out to 0. read mode (rwn = 1): the master generates 16 clock cycles at sclout in total. it outputs 8 bits (msb first) to the sdaout line at the falling edge of the clock. the sdaout line is released after the rwn bit has been transmitted. the slave outputs 8 bits of data (msb first) at rising edge of the clock. the master samples sdaout at the falling edge of sclout. the master closes the trans - mission by setting the csel1out and csel2out to 0. table 5. 3-wire transaction detailfigure 13. 3-wire interface timing diagram bit name description 15:9 address 7-bit internal register address 8 rwn 0: write, 1: read 7:0 data 8-bit read or write data csel_out sclout sdaout csel_outnote: see the 3-wire digital interface specification table for details. csel_out implies csel1out or csel2out. sclout sdaout 12 34 5678 a6 91 01 112131 41 5 0 12 34 5678 91 01 112131 41 5 0 a5 a4 a3 a2 a1 rwn d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 rwn write moderead mode a0 a6 a5 a4 a3 a2 a1 a0 t l t ch t cl t ch t cl t l t ds t dh t ds t rs t dh t t t t downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 29 maxim integrated 3-wire slave register map and ds1886 corresponding location when the max3945 registers are written, the max3710 are also written simultaneously ( table 6 ). 3-wire master flowchart figure 14 explains the working of the 3-wire master in the ds1886 in all three opreating modes. these modes are described in the ds1886 with max3710 operating modes section. table 6. 3-wire register map and ds1886 corresponding location ds1886 register (a2h table 02h) ds1886 register name max3710 address max3710 register name max3945 address max3945 register name 82h?83h modulation value 0eh set_imod n/a n/a 85h apc value 11h set_2xapc n/a n/a 86h?87h set_bias value 0dh set_ibias n/a n/a cah incbyte[7:4] 0fh biasinc n/a n/a cah incbyte[3:0] 10h modinc n/a n/a cbh txctrl5 dpc 0ah txctrl5 n/a n/a cch imodmax 0ch imodmax n/a n/a cdh ibiasmax 0bh ibiasmax n/a n/a e0h rxctrl1 01h rxctrl1 00h rxctrl1 e1h rxctrl2 02h rxctrl2 01h rxctrl2 e2h setcml 03h set_cml 03h set_cml e3h setlosh 04h set_los n/a n/a e4h txctrl1 06h txctrl1 n/a n/a e5h txctrl2 07h txctrl2 n/a n/a e6h txctrl3 08h txctrl3 n/a n/a e7h txctrl4 09h txctrl4 n/a n/a e8h txctrl5 apc ol 0ah txctrl5 n/a n/a e9h txctrl6 13h txctrl6 n/a n/a eah txctrl7 05h txcfg n/a n/a ech setlosh_3945 n/a n/a 04h set_los edh setlosl_3945 n/a n/a 04h set_los eeh setlostimer_3945 n/a n/a 12h set_lostimer f0h 3wctrl manual control of read/write from/to 3-wire slave devices; useful for determining correct settings for the slave devices and also for debugging. f1h address f2h write f3h read f4h txstat2 1fh txstat2 n/a n/a f5h txstat1 1eh txsta1 n/a n/a f6h dpcstat 1dh dpcstat n/a n/a f7h rxstat 1ch rxstat n/a n/a downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 30 maxim integrated figure 14. 3-wire flowchart txd = 1 or por = 1 en_3945 = 1? reset (set txd_flag if txd = 1 and set por_flag if por = 1) y y n write control rxctrl1, rxctrl2, set_cml, set_los, txctrl1, txctrl2, txctrl3, txctrl4 idle wait for temp_conv write txctrl6 rstrt_3710txinlos write_lut registers txctrl5 imodmax ibiasmax set_imod set_ibias biasinc modinc set_2xapc write cntrl max3945 read txstat1 inc apc inc mod temp_conv = 1? txd_standby toggle monsel write all control registers if enabled write registers ibiasmax imodmax txctrl5 manmode allows the user to communicate with max3710 using the i 2 c interface on ds1886 steady state (fig 15) toggle monsel bit (txctrl2[6]) periodically; reset flags txd_flag = 1? txstat1 = ffh? v cc > vcc lo? y y y n txd = 0? y n n y n y y n n n por_flag* = 1? a *por_flag is set by a por. this flag is reset in the steady state. y n burst_mode = 1 and md1regh <17? n y por_flag = 1? manmode = 1? manmode = 1? apc_en = 1? txd_flag = 1? apc_en = 1? write modinc, set_imod biasinc, set_ibias write modinc, set_imod y dpc_en = 1? n inc bias, mod n y dpc_en = 1? temp_conv = 1? and dis3w = 0 rstrt_3710 = 1 or txf_latched = 1 temp_conv = 1 and dis3w = 0 n n y n y y y a read registers bias reg, mod reg, rxstat, dpcstat, txstat1, txstat2, md0regh,md1regh, set_2xapc downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 31 maxim integrated 3-wire power-on reset the ds1886 detects whether a power-on reset has occured on the slave 3-wire device. this is done using the flowchart shown in figure 15 . figure 15. max3710 brownout detection flowchart write_control rxctrl1, rxctrl2, set_cml, set_los, txctrl1, txctrl2, txctrl3, txctrl4 read txstat1 write_lut registers txctrl5, imodmax, ibiasmax, set_imod, set_ibias, modinc, biasinc, set_2xapc steady state fault wait state 1, 2 txf = 1? write txctrl6 yes txf = 1? yes temp conversion complete? no txstat1 = ffh? no no no write_lut registers txctrl5, imodmax, ibiasmax, set_imod, set_ibias, modinc, biasinc, set_2xapc note 1: fault wait state has access to max3710 in manual mode. note 2: mon_sel bit is toggled as needed to keep the txp/txb monitors correct. yes yes write txctrl6 txf = 1? no yes downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 32 maxim integrated ds1886 with max3710 operating modes the user has the option of selecting among open loop, apc loop, and dual closed-loop operation modes. these can be programmed using the dpc_en and apc_en bits in the max3710 txctrl3 register (address h0x08), programmed through a2h table 02h, register e6h . table 7 indicates what the values in each lut cor - responds to in each of the modes. lut values are not automatically updated when changing between operat - ing modes. open loop mode, dpc_en = 0, apc_en = 0 in open loop mode, the laser bias and modulation are both controlled using luts. each lut consists of an 8-bit lut with up to 2 n c temperature resolution and an 8-bit offset lut. this allows the ds1886 to fully support the 10-bit bias dac and 9-bit modulation dac inside the max3710. apc loop mode, dpc_en = 0, apc_en = 1 in apc loop or single closed-loop mode, the laser bias is controlled by an apc loop, while the modulation is controlled using a temperature-indexed lut. the apc setpoint is controlled using an lut having up to 16 n c resolution. the apc loop initial value (set_ibias) is set using an lut having up to 2 n c resolution. the modula - tion lut consists of an 8-bit lut with up to 2 n c tempera - ture resolution and an 8-bit offset lut. this allows the ds1886 to fully support the 10-bit bias dac and 9-bit modulation dac inside the max3710. dual closed-loop mode, dpc_en = 1, apc_en = 1 in dual closed-loop mode, the laser bias is controlled by an apc loop, while the modulation is controlled with an extinction ratio loop. the apc setpoint and extinction ratio setpoints are controlled using 8-bit luts with up to 2 n c temperature resolution and 8-bit offset luts. each loop is initialized using 8-byte luts. table 7. ds1886 lut functions in open loop, apc loop, and dual closed-loop modes table register open loop apc loop dual closed loop 04h 80h?a7h 8-bit modulation value [7:0] 8-bit modulation value [7:0] 8-bit txctrl5[7:0] f0h?f7h imodmax[8:1] imodmax[8:1] imodmax[8:1] f8h?ffh modulation offset [9:2] modulation offset [9:2] set_imod[8:1](mod initial value) 06h 80h?a7h 8-bit bias value [7:0] 8-bit set_ibias [9:2] 8-bit set_ibias [9:2] f0h?f7h ibiasmax[9:2] ibiasmax[9:2] ibiasmax[9:2] f8h?ffh bias offset [9:2] 8-bit apc value [7:0] 8-bit apc value [7:0] 08h f8h?ffh incbyte (set to all zeros) incbyte7:4 = biasinc 3:0 = modinc (set to all zeros) incbyte7:4 = biasinc 3:0 = modinc downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 33 maxim integrated table 8. ds1886 lut memory map for 5-row table (temperature values indicated in c) table 9. ds1886 lut memory map for 5-row table (tindex values indicated in hex) bias, modulation, set_2xapc, txctrl5 luts luts allow temperature indexing the bias and modulation values and their respective offsets. depending on the operation mode (see the ds1886 with max3710 operating modes section), the luts function differently, as indicated in table 7 . the luts have nonlinear temperature indexing. after every temperature conversion, based on the internal tem - perature read, a tindex value is calculated, which then indexes the lut. the luts can index with a resolution as low as 2 n c. this is illustrated in table 8 and table 9 . bias, modulation and txctrl5 are 5-row luts. further details can be found in the lut descriptions. row byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 80h -40 -32 -24 -16 -8 0 +8 +16 88h +24 +28 +32 +36 +40 +44 +48 +52 90h +56 +58 +60 +62 +64 +66 +68 +70 98h +72 +74 +76 +78 +80 +82 +84 +86 a0h +88 +90 +92 +94 +96 +98 +100 +102 row byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 80h 80 84 88 8c 90 94 98 9c 88h a0 a2 a4 a6 a8 aa ac ae 90h b0 b1 b2 b3 b4 b5 b6 b7 98h b8 b9 ba bb bc bd be bf a0h c0 c1 c2 c3 c4 c5 c6 c7 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 34 maxim integrated the offsets are also temperature indexed. figure 16 illus - trates how the offsets would affect the final output as the temperature varies. table 10 shows the temperature resolution for the offsets. modulation value figure 17 shows how to calculate the modulation value that is recalled from the lut and sent to the max3710. bias value figure 18 shows how to calculate the bias value that is recalled from the lut and sent to the max3710. figure 16. offset lut figure 17. modulation lut (open loop and apc mode) figure 18. bias lut (open loop) table 10. temperature resolution for offsets row byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 f8h -40 n c -8 n c +8 n c +24 n c +40 n c +56 n c +72 n c +88 n c 9 mod offset[9:2] ds1886 modulation value pow_lev [1:0] 8 7 6 5 4 3 2 1 mod[7:0] 0 7 6 5 4 3 2 max3710set_imod[8:0] gain power level (db) 00 1* 0 01 0.5 -3 1x 0.25 -6 krmd[2:1] (max3710) 1x 01 00 txctrl3 1x 01 00 0 255 511 value determined by luts with corresponding offset luts 767 1023 each offset register can be independently set between0 and 1020. 1020 = 4 x ffh. this example illustrates positive and negatve tempco. lut bits 7:0 f8h lut bits 7:0 f9h lut bits 7:0 fah lut bits 7:0 fbh lut bits 7:0 fch lut bits 7:0 fdh lut bits 7:0 feh lut bits 7:0 ffh 0 255 511 -40c -8c +8c +24c +40c offset luts [8 registers] offset luts [8 registers] +56c +72c +88c +104c value determined by luts with corresponding offset luts 767 1023 each offset register can be independentlyset between 0 and 1020. 1020 = 4 x ffh. this example illustrates positive tempco. lut bits 7:0 f8h lut bits 7:0 f9h lut bits 7:0 fah lut bits 7:0 fbh lut bits 7:0 fch lut bits 7:0 fdh lut bits 7:0 feh lut bits 7:0 ffh -40c -8c +8c +24c +40c +56c +72c +88c +104c 9 bias offset[9:2] the bias value that is recalled from the lut and sent to the max3710 is calculated as follows: 8 7 6 5 4 3 2 1 bias[7:0] 0 7 6 5 4 3 2 max3710set_ibias[9:0] downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 35 maxim integrated power leveling the ds1886 supports power leveling as described in g.984.2. the pow_lev[1:0] bits in update a2h lower memory, register 6fh allow for three power level set - tings: 0db, -3db, and -6db. depending on the operation mode, a combination of set_imod and the krmd bits (max3710 txctrl3 register) are adjusted to meet these power-level settings. the krmd bits adjust the gain of the apc loop and extinction ratio loop. see table 11a and table 11b . manual max3710 operations the master interface is controllable using four registers in the ds1886: 3wctrl, address, write, read. commands can be manually issued while the ds1886 is in normal operation mode. it is also possible to suspend normal 3-wire commands so that only manual operation commands are sent (3wctrl, a2h table 04h, register f8h?ffh ). i 2 c communication i 2 c definition the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the master?s request. bus idle or not busy: time between stop and start conditions when both sda and scl are inac - tive and in their logic-high states.start conditi on: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see figure 19 for applicable timing.stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see figure 19 for applicable timing.repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data trans - fer following the current one. repeated starts are com - monly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a normal start condition. see figure 19 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements ( figure 19 ). data is shifted into the device during the rising edge of the scl. bit read: at the end a write operation, the master must release the sda bus line for the proper amount of setup time before the next rising edge of scl during table 11a. power leveling details (when ds1863_mode = 0, default)table 11b. power leveling details (when ds1863_mode = 1) power level (db) pow_lev[1:0] (register 6fh) modulation change krmd[2:1] (max3710) txctrl3 pow_lev_init 0 00 none 1x 1x -3 01 right-shift set_imod once 01 01 -6 1x right-shift set_imod twice 00 00 power level (db) pow_lev_ds1863[2:0] (register 8ch) modulation change krmd[2:1] (max3710) 0 000?010 none 1x -3 011?110 right-shift set_imod once 01 -6 111 right-shift set_imod twice 00 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 36 maxim integrated a bit read ( figure 19 ). the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master gener - ates all scl clock pulses, including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowl - edgement (ack) or not-acknowledge (nack) is always the 9th bit transmitted during a byte trans - fer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device performs a nack by transmitting a one during the 9th bit. timing for the ack and nack is identical to all other bit writes ( figure 19 ). an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of informa - tion transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the ds1886 responds to two slave addresses. the auxiliary memory always responds to a fixed i 2 c slave address, a0h. the lower memory and tables 00h?08h respond to i 2 c slave addresses that can be configured to any value between 00h?feh using the device address byte ( a2h table 02h, register 8ch ). the user also must set the asel bit ( a2h table 02h, register 89h ) for this address to be active. by writing the correct slave address with r/ w = 0, the master indi - cates that it would write data to the slave. if r/ w = 1, the master reads data from the slave. if an incorrect slave address is written, the device assumes the master is communicating with another i 2 c device and ignores the communications until the next start condition is sent. if the main device?s slave address is programmed to be a0h, access to the auxiliary memory is disabled. memory address: during an i 2 c write operation to the device, the master must transmit a memory address to identify the memory location where the slave is to store figure 19. i 2 c timing diagram sclnote: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 37 maxim integrated the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. i 2 c protocol see figure 20 for an example of i 2 c timing. writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember that the master must read the slave?s acknowledgement during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start condi - tion, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 8 data bytes, and gener - ates a stop condition. the device writes 1 to 8 bytes (one page or row) with a single write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. the address counter limits the write to one 8-byte page (one row of the memory map). attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the pres - ent row.for example: a 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three ?consecutive? addresses. the result is that addresses 06h and 07h would contain 11h and 22h, respec - tively, and the third data byte, 33h, would be written to address 00h. to prevent address wrapping from occurring, the mas - ter must send a stop condition at the end of the page, then wait for the bus free time or eeprom write time to elapse. then the master can generate a new start condition and write the slave address byte (r/ w = 0) and the first memory address of the next memory row before continuing to write data. figure 20. example i 2 c timing start start stop slave ack slave ack stop single-byte write-write 00h to register bah two-byte write -write 01h and 75h to c8h and c9h single-byte read-read register bah two-byte read -read c8h and c9h repeated start master nack 10100010 a2h 10111010 bah slave ack start slave ack 10100010 a2h 1010001 1 a3h 10111010 bah slave ack slave ack stop 00000000 00h stop slave ack stop 01110101 75h start slave ack 10100010 a2h 11001000 c8h slave ack slave ack 00000001 01h slave ack data in bah data repeated start master ack start slave ack 10100010 a2h 1010001 1 a3h 11001000 c8h slave ack slave ack data in c8h data master nack data in c9h data example i 2 c transactions with a2h as the main memory device address *if asel is 0, the slave address is a0h for the auxiliary memory and a2h for the main memory.if asel = 1, the slave address is determined by table 02h, register 89h for the main memory. the auxiliary memory continues to be addressed at a0h, except when the programmed address for the main memory is a0h. typical i 2 c write transaction a)c) b)d) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 register address msb lsb b7 b6 b5 b4 b3 b2 b1 b0 data slave ack slave ack slave address* 1 0 1 0 0 0 1 r/w msb lsb read/ write downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 38 maxim integrated acknowledge polling: any time a eeprom page is written, the device requires the eeprom write time (t w ) after the stop condition to write the contents of the page to eeprom. during the eeprom write time, the device does not acknowledge its slave address because it is busy. it is possible to take advantage of that phenomenon by repeatedly addressing the device, which allows the next page to be written as soon as the device is ready to receive the data. the alternative to acknowledge polling is to wait for maxi - mum period of t w to elapse before attempting to write again to the device.eeprom write cycles: when eeprom writes occur, the device writes the whole eeprom memory page, even if only a single byte on the page was modified. writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. because the whole page is written, bytes on the page that were not modified during the transaction are still subject to a write cycle. this can result in a whole page being worn out over time by writing a single byte repeatedly. writing a page 1 byte at a time wears the eeprom out 8x faster than writing the entire page at once. the device?s eeprom write cycles are specified in the nonvolatile memory characteristics table. the specification shown is at the worst-case temperature. it can handle approximately 10x that many writes at room temperature. writing to sram-shadowed eeprom memory with seeb = 1 does not count as a eeprom write cycle when evaluat - ing the eeprom?s estimated lifetime.reading a single byte from a slave: unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and gener - ates a stop condition.manipulating the address counter for reads: a dummy write cycle can be used to force the address pointer to a particular value. to do this, the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condi - tion, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. memory organization the following sections provide the device?s register definitions (see figure 21 for the memory map). each register or row of registers has an access descriptor that determines the password level required to read or write the memory. level 2 password is intended for the mod - ule manufacture access only; level 1 password allows another level of protection for items the end consumer may wish to protect. many registers are always readable, but require password access to write. there are a few registers that cannot be read without password access. the below access codes describe each mode used by the ds1886 with factory setting for the pw_ena ( a2h table 02h, register c0h ) and pw_enb ( a2h table 02h, register c1h ) values set to factory settings. access code read access write access <0> at least 1 byte/bit in the row/byte is different than the rest of the row/byte, so look at each byte/bit separately for permissions. <1> read all write pw2 <2> read all write not applicable <3> read all write all, but the device hardware also writes to these bytes/bits <4> read pw2 write pw2 + mode_bit <5> read all write all <6> read not applicable write all <7> read pw1 write pw1 <8> read pw2 write pw2 <9> read not applicable write pw2 <10> read pw2 write not applicable <11> read all write pw1 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 39 maxim integrated figure 21. memory organization eeprom (256 bytes) ffh i 2 c address a0h i 2 c address a2h auxiliary device main device 00h alarm- enable row (8 bytes) password entry (pwe) (4 bytes) table select byte ffh 80hf8h mod max lut mod offset/ set_imod lut ffh f0h table 01h eeprom (120 bytes) f7h 7fh 00h lower memory 3w config ffh 80he0h table 05h ffh f8h table 02h nonlookup table control and configuration registers e7h biasinc lut modinc lut ffh 80hf8h table 08h 80h table 04h modulation/ txctrl5 lut eeprom note: alarm enable row can be configured to exist at table 01h or table 05h using mask bit in registers 89h, table 02h. a7h bias max lut bias offset/ apc lut ffh f0h dac offset lut ffh 80hf8h table 09h 80h table 06h bias/set_ibias lut eeprom a7h downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 40 maxim integrated register descriptions the register maps show each byte/word (2 bytes) in terms of its row in the memory. the first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. each subsequent byte on the row is one/two memory locations beyond the previous byte/word?s address. a total of 8 bytes are present on each row. for more information about each of these bytes, see the corresponding register description. a2h lower memory register map a2h table 01h register map the access codes represent the factory default values of pw_ena ( a2h table 02h, register c0h ) and pw_enb ( a2h table 02h, register c1h ). note: the alarm enable bytes (registers f8h ? ffh) can be configured to exist in a2h table 05h instead of here at a2h table 01h with the mask bit ( a2h table 02h, register 89h ). if the row is configured to exist in a2h table 05, then these locations are ee in a2h table 01h. lower memory row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00 <1> threshold 0 temp alarm hi temp alarm lo temp warn hi temp warn lo 08 <1> threshold 1 v cc alarm hi v cc alarm lo v cc warn hi v cc warn lo 10 <1> threshold 2 txb alarm hi txb alarm lo txb warn hi txb warn lo 18 <1> threshold 3 txp alarm hi txp alarm lo txp warn hi txp warn lo 20 <1> threshold 4 rssi alarm hi rssi alarm lo rssi warn hi rssi warn lo 28?37 empty empty empty empty empty empty empty empty empty 38?5f <1> eeprom ee ee ee ee ee ee ee ee 60 <2> adc values 0 temp value v cc value txb value txp value 68 <0> adc values 1 <2> rssi value <2> reserved <2> reserved <0> status <3> update 70 <5> alarm/warn alarm 3 alarm 2 reserved reserved warn 3 warn 2 reserved reserved 78 <0> table select <5> reserved <5> reserved <5> reserved <6> pwe msw <6> pwe msw <6> pwe lsw <6> pwe lsw <5> tbl sel access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access see each bit/byte separately all all all pw2 all n/a pw1 pw2 n/a pw2 all write access pw2 n/a all and device hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 a2h table 01h row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80?bf <7> eeprom ee ee ee ee ee ee ee ee c0?f7 <8> eeprom ee ee ee ee ee ee ee ee f8 <8> alarm enable alarm en 3 alarm en 2 reserved reserved warn en 3 warn en 2 reserved reserved downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 41 maxim integrated a2h table 02h register map * the final result must be xored with bb40h before writing to this register. ** do not write to this register. the access codes represent the factory default values of pw_ena ( a2h table 02h, register c0h ) and pw_enb ( a2h table 02h, register c1h ). a2h table 02h (pw2) row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <0> config 0 <8> mode <4> tindex <4> modulation value reserved <4> apc value <4> set_ibias value 88 <8> config 1 dacfs cnfga cnfgb cnfgc reserved cnfgd rshift 1 rshift 0 90 <8> scale 0 xover coarse v cc scale txb scale txp scale 98 <8> scale 1 rssi fine scale reserved rssi coarse scale reserved a0 <8> offset 0 xover fine v cc offset txb offset txp offset a8 <8> offset 1 rssi fine offset reserved rssi coarse offset internal temp offset* b0 <9> pwd value pw1 msw pw1 lsw pw2 msw pw2 lsw b8 empty empty empty empty empty empty empty empty empty c0 <8> pwd enable pw_ena pw_enb reserved reserved reserved reserved reserved tblselpon c8 <0> maxrow <4> dac value <4> dac value <4> incbyte <4> txctrl5 dpc <4> imodmax <4> ibiasmax <10> device id <10> device ver d0?df empty empty empty empty empty empty empty empty empty e0 <8> 3w config 0 rxctrl1 rxctrl2 setcml setlosh txctrl1 txctrl2 txctrl3 txctrl4 e8 <8> 3w config 1 txctrl5 apc ol txctrl6 txctrl7 reserved setlosh_3945 setlosl_3945 set_los timer_3945 3wset f0 <0> 3w config 2 <8> 3wctrl <8> address <8> write <10> read <10> txstat2 <10> txstat1 <10> dpcstat <10> rxstat f8 empty empty empty empty empty empty empty empty empty access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access see each bit/byte separately all all all pw2 all n/a pw1 pw2 n/a pw2 all write access pw2 n/a all and device hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 42 maxim integrated a2h table 04h register mapa2h table 05h register map a2h table 06h register map note: a2h table 05h is empty by default. it can be configured to contain the alarm and warning enable bytes from a2h table 01h, registers f8h-ffh with the mask bit enabled (a2h table 02h, register 89h). in this case a2h table 01h will be empty. the access codes represent the factory default values of pw_ena ( a2h table 02h, register c0h ) and pw_enb ( a2h table 02h, register c1h ). access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access see each bit/byte separately all all all pw2 all n/a pw1 pw2 n/a pw2 all write access pw2 n/a all and device hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 a2h table 04h (modulation or txctrl5 lut) row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80?a7 <8> modulation/ txctrl5 see table description a8?ef empty empty empty empty empty empty empty empty empty f0 <8> imodmax mod max lut mod max lut mod max lut mod max lut mod max lut mod max lut mod max lut mod max lut f8 <8> mod offset/ set_imod lut see table description a2h table 05h row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80?f7 empty empty empty empty empty empty empty empty empty f8 <8> alarm enable alarm en 3 alarm en 2 reserved reserved warn en 3 warn en 2 reserved reserved a2h table 06h (bias or apc lut) row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80?a7 <8> bias/apc lut see table description a8?ef empty empty empty empty empty empty empty empty empty f0 <8> ibiasmax bias max lut bias max lut bias max lut bias max lut bias max lut bias max lut bias max lut bias max lut f8 <8> bias/set_ibias off see table description downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 43 maxim integrated a2h table 08h register mapa2h table 09h register map auxiliary a0h memory register map the access codes represent the factory default values of pw_ena ( a2h table 02h, register c0h ) and pw_enb ( a2h table 02h, register c1h ). a2h table 08h (inc lut) row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80?f7 empty empty empty empty empty empty empty empty empty f8?ff <8> incrow incbyte incbyte incbyte incbyte incbyte incbyte incbyte incbyte a2h table 09h (dac offset lut) row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80?f7 empty empty empty empty empty empty empty empty empty f8?ff <8> dac offset dacoff dacoff dacoff dacoff dacoff dacoff dacoff dacoff auxiliary memory (a0h) row (hex) row name word 0 word 1 word 2 word 3 byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00?7f <5> aux ee ee ee ee ee ee ee ee ee 80?ff <5> aux ee ee ee ee ee ee ee ee ee access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access see each bit/byte separately all all all pw2 all n/a pw1 pw2 n/a pw2 all write access pw2 n/a all and device hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 44 maxim integrated a2h lower memory register descriptions a2h lower memory, register 00h?01h: temp alarm hia2h lower memory, register 04h?05h: temp warn hi a2h lower memory, register 02h?03h: temp alarm lo a2h lower memory, register 06h?07h: temp warn lo factory default 7fffh read access all write access pw2 memory type nonvolatile (see) 00h, 04h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 01h, 05h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 temperature measurement updates above this two?s complement threshold set its corresponding alarm or warning bit. temperature measurement updates equal to or below this threshold clear its alarm or warning bit. factory default 8000h read access all write access pw2 memory type nonvolatile (see) 02h, 06h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 03h, 07h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 temperature measurement updates below this two?s complement threshold set its corresponding alarm or warning bit. temperature measurement updates equal to or above this threshold clear its alarm or warning bit. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 45 maxim integrated a2h lower memory, register 08h?09h: v cc alarm hi a2h lower memory, register 0ch?0dh: v cc warn hi a2h lower memory, register 10h?11h: txb alarm hia2h lower memory, register 14h?15h: txb warn hi a2h lower memory, register 18h?19h: txp alarm hi a2h lower memory, register 1ch?1dh: txp warn hi a2h lower memory, register 20h?21h: rssi alarm hi a2h lower memory, register 24h?25h: rssi warn hi factory default ffffh read access all write access pw2 memory type nonvolatile (see) 08h, 0ch, 10h,14h, 18h, 1ch, 20h, 24h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 09h, 0dh, 11h, 15h, 19h, 1dh, 21h, 25h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit. voltage measurements equal to or below this threshold clear its alarm or warning bit. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 46 maxim integrated a2h lower memory, register 0ah?0bh: v cc alarm lo a2h lower memory, register 0eh?0fh: v cc warn lo a2h lower memory, register 12h?13h: txb alarm loa2h lower memory, register 16h?17h: txb warn lo a2h lower memory, register 1ah?1bh: txp alarm lo a2h lower memory, register 1eh?1fh: txp warn lo a2h lower memory, register 22h?23h: rssi alarm lo a2h lower memory, register 26h?27h: rssi warn lo factory default 0000h read access all write access pw2 memory type nonvolatile (see) 0ah, 0eh, 12h, 16h, 1ah, 1eh, 22h, 26h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 0bh, 0fh, 13h, 17h, 1bh, 1fh, 23h, 27h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. voltage measurements equal to or above this threshold clear its alarm or warning bit. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 47 maxim integrated a2h lower memory, register 28h?37h: emptya2h lower memory, register 38h?5fh: ee a2h lower memory, register 60h?61h: temp value factory defaultread access n/a write access n/a memory type these registers are empty. factory default 00h read access all write access pw2 memory type nonvolatile (ee) 38h?5fh ee ee ee ee ee ee ee ee bit 7 bit 0 pw2 level access-controlled eeprom. factory default 0000h read access all write access n/a memory type volatile 60h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 61h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 signed two?s complement direct-to-temperature measurement. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 48 maxim integrated a2h lower memory, register 62h?63h: v cc value a2h lower memory, register 64h?65h: txb valuea2h lower memory, register 66h?67h: txp value a2h lower memory, register 68h?69h: rssi value a2h lower memory, register 6ah?6dh: reserved power-on value 0000h read access all write access n/a memory type volatile 62h, 64h, 66h, 68h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 63h, 65h, 67h, 69h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 left-justified unsigned voltage measurement. power-on value 00h read access n/a write access n/a memory type these registers are reserved. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 49 maxim integrated a2h lower memory, register 6eh: status power-on value x0xx 0xxxb read access all write access see below description memory type volatile write access n/a all n/a all all n/a n/a n/a 6eh txds txdc txfis rsels reserved txfouts rxl rdyb bit 7 bit 0 bit 7 txds: txd status bit. reflects the logic state of the txd pin (read-only). 0 = txd pin is logic-low.1 = txd pin is logic-high. bit 6 txdc: txd software control bit. this bit allows for software control that is identical to the txd pin. see the section on txd for further information. its value is wired-ored with the logic value of the txd pin (writable by all users). 0 = (default) 1 = forces the device into a txd state regardless of the value of the txd pin. bit 5 txfis: reflects the status of the txf pin. the status will also include any inversion caused by the invtxfi bit (read-only).0 = txf pin is low (after any inversion caused by the invtxfi bit). 1 = txf pin is high (after any inversion caused by the invtxfi bit). bit 4 rsels: rsel status bit. reflects the logic state of the rsel pin (read-only). 0 = rsel pin is logic-low.1 = rsel pin is logic-high. bit 3 reserved bit 2 txfouts: txfout status. indicates the state the open drain output is attempting to achieve. 0 = txfout is pulling low.1 = txfout is high impedance. bit 1 rxl: reflects the driven state of the los pin (read-only). 0 = los pin is driven low.1 = los pin is pulled high. bit 0 rdyb: ready bar. 0 = v cc is above poa. 1 = v cc is below poa and/or too low to communicate over the i 2 c bus. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 50 maxim integrated a2h lower memory, register 6fh: update power-on value 00h read access all write access all and ds1886 hardware memory type volatile 6fh temp rdy vcc rdy txb rdy txp rdy rssi rdy rssir pow_lev1 pow_lev0 bit 7 bit 0 bits 7:3 update of completed conversions. at power-on, these bits are cleared and are set as each conversion is completed. these bits can be cleared so that a completion of a new conversion is verified. bit 2 rssir: rssi range. reports the range used for conversion update of rssi. 0 = fine range is the reported value.1 = coarse range is the reported value. bits 1:0 pow_lev[1:0]: power level. these bits are active only when the ds1863_mode bit in a2h table 02h, register 8dh (cnfgd) is 0. these bits change the max3710 bits krmd[2:1] to adjust the md input impedance. see the power leveling section for more details. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 51 maxim integrated a2h lower memory, register 70h: alarm 3 power-on value 10h read access all write access n/a memory type volatile 70h temp hi temp lo vcc hi vcc lo txb hi txb lo txp hi txp lo bit 7 bit 0 bit 7 temp hi: high alarm status for temperature measurement. 0 = (default) last measurement was equal to or below threshold setting.1 = last measurement was above threshold setting. bit 6 temp lo: low alarm status for temperature measurement. 0 = (default) last measurement was equal to or above threshold setting.1 = last measurement was below threshold setting. bit 5 vcc hi: high alarm status for v cc measurement. 0 = (default) last measurement was equal to or below threshold setting1 = last measurement was above threshold setting. bit 4 vcc lo: low alarm status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it clears itself when a v cc measurement is completed and the value is above the low threshold.0 = last measurement was equal to or above threshold setting. 1 = (default) last measurement was below threshold setting. bit 3 txb hi: high alarm status for txb measurement. 0 = (default) last measurement was equal to or below threshold setting.1 = last measurement was above threshold setting. bit 2 txb lo: low alarm status for txb measurement. 0 = (default) last measurement was equal to or above threshold setting.1 = last measurement was below threshold setting. bit 1 txp hi: high alarm status for txp measurement. 0 = (default) last measurement was equal to or below threshold setting.1 = last measurement was above threshold setting. bit 0 txp lo: low alarm status for txp measurement. 0 = (default) last measurement was equal to or above threshold setting.1 = last measurement was below threshold setting. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 52 maxim integrated a2h lower memory, register 71h: alarm 2 a2h lower memory, register 72h?73h: reserved power-on value 00h read access all write access n/a memory type volatile 71h rssi hi rssi lo reserved reserved reserved in1s reserved txfint bit 7 bit 0 bit 7 rssi hi: high alarm status for rssi measurement. a txd event does not clear this alarm. 0 = (default) last measurement was equal to or below threshold setting.1 = last measurement was above threshold setting. bit 6 rssi lo: low alarm status for rssi measurement. a txd event does not clear this alarm. 0 = (default) last measurement was equal to or above threshold setting.1 = last measurement was below threshold setting. bits 5:3 reserved bit 2 in1s: in1 status bit. reflects the logic state of the in1 pin (read-only). 0 = in1 pin is logic-low.1 = in1 pin is logic-high. bit 1 reserved bit 0 txfint: txfout interrupt. this bit is the wired-ored logic of all alarms and warnings wired-anded with their corresponding enable bits. the enable bits are found in a2h table 01h/05h, registers f8?ffh. power-on value 00h read access all write access n/a memory type these registers are reserved. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 53 maxim integrated a2h lower memory, register 74h: warn 3 power-on value 10h read access all write access n/a memory type volatile 74h temp hi temp lo vcc hi vcc lo txb hi txb lo txp hi txp lo bit 7 bit 0 bit 7 temp hi: high warning status for temperature measurement. 0 = (default) last measurement was equal to or below threshold setting.1 = last measurement was above threshold setting. bit 6 temp lo: low warning status for temperature measurement. 0 = (default) last measurement was equal to or above threshold setting.1 = last measurement was below threshold setting. bit 5 vcc hi: high warning status for v cc measurement. 0 = (default) last measurement was equal to or below threshold setting.1 = last measurement was above threshold setting. bit 4 vcc lo: low warning status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it clears itself when a v cc measurement is completed and the value is above the low threshold.0 = last measurement was equal to or above threshold setting. 1 = (default) last measurement was below threshold setting. bit 3 txb hi: high warning status for txb measurement. 0 = (default) last measurement was equal to or below threshold setting.1 = last measurement was above threshold setting. bit 2 txb lo: low warning status for txb measurement. 0 = (default) last measurement was equal to or above threshold setting.1 = last measurement was below threshold setting. bit 1 txp hi: high warning status for txp measurement. 0 = (default) last measurement was equal to or below threshold setting.1 = last measurement was above threshold setting. bit 0 txp lo: low warning status for txp measurement. 0 = (default) last measurement was equal to or above threshold setting.1 = last measurement was below threshold setting. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 54 maxim integrated a2h lower memory, register 75h: warn 2 a2h lower memory, register 76h?7ah: reserved power-on value 00h read access all write access n/a memory type volatile 75h rssi hi rssi lo reserved reserved reserved reserved reserved reserved bit 7 bit 0 bit 7 rssi hi: high warning status for rssi measurement. 0 = (default) last measurement was equal to or below threshold setting.1 = last measurement was above threshold setting. bit 6 rssi lo: low warning status for rssi measurement. 0 = (default) last measurement was equal to or above threshold setting.1 = last measurement was below threshold setting. bits 5:0 reserved power-on value 00h read access n/a write access n/a memory typethese registers are reserved. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 55 maxim integrated a2h lower memory, register 7bh?7eh: password entry (pwe)a2h lower memory, register 7fh: tbl sel power-on value ffff ffffh read access n/a write access all memory type volatile 7bh 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 7ch 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 7dh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 7eh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 there are two passwords for the ds1886. each password is 4 bytes long. the lower level password (pw1) will have all the access of a normal user plus those made available with pw1. the higher level password (pw2) will have all of the access of pw1 plus those made available with pw2. the values of the passwords reside in eeprom inside of pw2 memory. at power up, all pwe bits are set to 1. all reads at this location are 0. power-on value tblselpon (a2h table 02h, register c7h). read access all write access all memory type volatile 7fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the upper memory tables of the ds1886 are accessible by writing the desired table value in this register. the power-on value of this register is defined by the value written to tblselpon (a2h table 02, register c7h). downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 56 maxim integrated a2h table 01h register descriptions a2h table 05h can be configured to contain the alarm and warning enable bytes from a2h table 01h, registers f8h? ffh with the mask bit enabled ( a2h table 02h, register 89h ). in this case the corresponding bytes in a2h table 01h are empty.a2h table 01h, register 80h?bfh: eeprom a2h table 01h, register c0h?f7h: eeprom power-on value 00h read access pw2 or (pw1 and rwtbl1a) or (pw1 and rtbl1a) write access pw2 or (pw1 and rwtbl1a) memory type nonvolatile (ee) 80h?bfh ee ee ee ee ee ee ee ee bit 7 bit 0 eeprom for pw1 and/or pw2 level access. power-on value 00h read access pw2 or (pw1 and rwtbl1b) or (pw1 and rtbl1b) write access pw2 or (pw1 and rwtbl1b) memory type nonvolatile (ee) c0h?f7h ee ee ee ee ee ee ee ee bit 7 bit 0 eeprom for pw1 and/or pw2 level access. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 57 maxim integrated a2h table 01h, register f8h: alarm en 3 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) f8h temp hi temp lo vcc hi vcc lo txb hi txb lo txp hi txp lo bit 7 bit 0 layout is identical to alarm 3 in lower memory, register 70h. enables alarms to create txfint (lower memory, register 71h) logic. the mask bit (a2h table 02h, register 89h) determines whether this memory exists in a2h table 01h or 05h. when in a2h table 05h, this location at a2h table 01h becomes ee. bit 7 temp hi:0 = disables interrupt from temp hi alarm. 1 = enables interrupt from temp hi alarm. bit 6 temp lo:0 = disables interrupt from temp lo alarm. 1 = enables interrupt from temp lo alarm. bit 5 vcc hi:0 = disables interrupt from vcc hi alarm. 1 = enables interrupt from vcc hi alarm. bit 4 vcc lo:0 = disables interrupt from vcc lo alarm. 1 = enables interrupt from vcc lo alarm. bit 3 txb hi:0 = disables interrupt from txb hi alarm. 1 = enables interrupt from txb hi alarm. bit 2 txb lo:0 = disables interrupt from txb lo alarm. 1 = enables interrupt from txb lo alarm. bit 1 txp hi:0 = disables interrupt from txp hi alarm. 1 = enables interrupt from txp hi alarm. bit 0 txp lo:0 = disables interrupt from txp lo alarm. 1 = enables interrupt from txp lo alarm. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 58 maxim integrated a2h table 01h, register f9h: alarm en 2 a2h table 01h, register fah?fbh: reserved power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) f9h rssi hi rssi lo reserved reserved reserved in1en reserved reserved bit 7 bit 0 layout is identical to alarm 2 in lower memory, register 71h. enables alarms to create txfint (lower memory, register 71h) logic. the mask bit (a2h table 02h, register 89h) determines whether this memory exists in a2h table 01h or 05h. when in a2h table 05h, this location at a2h table 01h becomes ee. bit 7 rssi hi:0 = disables interrupt from rssi hi alarm. 1 = enables interrupt from rssi hi alarm. bit 6 rssi lo:0 = disables interrupt from rssi lo alarm. 1 = enables interrupt from rssi lo alarm. bits 5:3 reserved bit 2 in1en0 = disable interrupt due to in1 input pin. 1 = enable interrupt due to in1 input pin. bit 0 reserved power-on value 00h read access n/a write access n/a memory type nonvolatile (see) these registers are reserved. when in a2h table 05h, this location at a2h table 01h becomes ee. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 59 maxim integrated a2h table 01h, register fch: warn en 3 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) fch temp hi temp lo vcc hi vcc lo txb hi txb lo txp hi txp lo bit 7 bit 0 layout is identical to warn 3 in lower memory, register 74h. enables warnings to create txfint (lower memory, register 71h) logic. the mask bit (a2h table 02h, register 89h) determines whether this memory exists in a2h table 01h or 05h. when in a2h table 05h, this location at a2h table 01h becomes ee. bit 7 temp hi:0 = disables interrupt from temp hi warning. 1 = enables interrupt from temp hi warning. bit 6 temp lo:0 = disables interrupt from temp lo warning. 1 = enables interrupt from temp lo warning. bit 5 vcc hi:0 = disables interrupt from vcc hi warning. 1 = enables interrupt from vcc hi warning. bit 4 vcc lo:0 = disables interrupt from vcc lo warning. 1 = enables interrupt from vcc lo warning. bit 3 txb hi:0 = disables interrupt from txb hi warning. 1 = enables interrupt from txb hi warning. bit 2 txb lo:0 = disables interrupt from txb lo warning. 1 = enables interrupt from txb lo warning. bit 1 txp hi:0 = disables interrupt from txp hi warning. 1 = enables interrupt from txp hi warning. bit 0 txp lo:0 = disables interrupt from txp lo warning. 1 = enables interrupt from txp lo warning. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 60 maxim integrated a2h table 01h, register fdh: warn en 2 a2h table 01h, register feh?ffh: reserved or ee power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) fdh rssi hi rssi lo reserved reserved reserved reserved reserved reserved bit 7 bit 0 layout is identical to warn 2 in lower memory, register 75h. enables warnings to create txfint (lower memory, register 71h) logic. the mask bit (a2h table 02h, register 89h) determines whether this memory exists in a2h table 01h or 05h. when in a2h table 05h, this location at a2h table 01h becomes ee. bit 7 rssi hi:0 = disables interrupt from rssi hi warning. 1 = enables interrupt from rssi hi warning. bit 6 rssi lo:0 = disables interrupt from rssi lo warning. 1 = enables interrupt from rssi lo warning. bits 5:0 reserved power-on value 00h read access n/a write access n/a memory type nonvolatile (see) these registers are reserved. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 61 maxim integrated a2h table 02h register descriptions a2h table 02h, register 80h: mode power-on value 7fh read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type volatile 80h seeb incrow lut en txctrl5 lut en bias lut en aen mod lut en apc lut en dac lut en bit 7 bit 0 bit 7 seeb:0 = (default) enables eeprom writes to see bytes. 1 = disables eeprom writes to see bytes during configuration, so that the configuration of the part is not delayed by the ee cycle time. once the values are known, write this bit to a 0 and write the see locations again for data to be written to the eeprom. bit 6 incrow lut en: 0 = incrow register is controlled by the user. the incrow register value is written with the use of the 3-wire interface. this allows users to interactively test their modules by writing the incrow register value. in apc loop mode, only biasinc[3:0] is updated. in dpc loop mode, both biasinc[3:0] and modinc[3:0] are updated. 1 = (default) enables auto control for the incrow register. bit 5 txctrl5 lut en:0 = txctrl5 dpc register is writable by the user and the lut recalls are disabled. 1 = (default) enables auto control of the lut for txctrl5. bit 4 bias lut en:0 = set_ibias and ibiasmax registers are controlled by the user. the set_ibias and ibiasmax value is written with the use of the 3-wire interface. this allows the user to interactively test their modules by directly controlling the set_ibias and ibiasmax. 1 = (default) enables lut control of the set_ibias and ibiasmax. bit 3 aen:0 = the temperature-calculated index value tindex is writable by the user and the updates of calculated indexes are disabled. this allows users to interactively test their modules by controlling the indexing for the look up tables. the recalled values from the luts appear in the dac registers after the next completion of a temperature conversion. 1 = (default) the internal temperature sensor determines the value of tindex bit 2 mod lut en:0 = modulation value and imodmax registers are controlled by the user. the modulation value and imodmax values are written with the use of the 3-wire interface. this allows users to interactively test their modules by directly controlling the modulation value and imodmax. 1 = (default) enables lut control of modulation value and imodmax. bit 1 apc lut en:0 = apc value register is controlled by the user. the apc value value is written with the use of the 3-wire interface. this allows users to interactively test their modules by directly controlling the apc value register. 1 = (default) enables lut control of apc value. bit 0 dac lut en: see the delta-sigma output and reference section for details. 0 = dac value is writable by the user and the dac formula calculation disabled. this allows users to interactively test their modules by writing the values for dac. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for dac value. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 62 maxim integrated a2h table 02h, register 81h: temperature index (tindex)a2h table 02h, register 82h?83h: modulation value a2h table 02h, register 84h: reserved factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access (pw2 and aen = 0) or (pw1 and rwtbl246 and aen = 0) memory type volatile 81h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 holds the calculated index based on the temperature measurement. this index is used for the address during lookup of tables 04h, 06h, and 08h. temperature measurements below -40 n c or above +102 n c are clamped to 80h and c7h, respectively. the calculation of tindex is as follows: temp_value 40 c tindex 80h 2c + = + for the temperature-indexed luts, the index used during the lookup function for each table is as follows:a2h table 04h (mod) 1 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 tindex 0 a2h table 06h (apc) 1 0 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 factory default 0000h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access (pw2 and mod lut en = 0) or (pw1 and rwtbl246 and mod lut en = 0) memory type volatile 82h 0 0 0 0 0 0 0 2 8 83h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for mod and recalled from a2h table 04h at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. factory default 00h read access n/a write access n/a memory type nonvolatile (see) this register is reserved. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 63 maxim integrated a2h table 02h, register 85h: apc valuea2h table 02h, register 86h?87h: set_ibias value a2h table 02h, register 88h: dacfs factory default 0000h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access (pw2 and apc lut en = 0) or (pw1 and rwtbl246 and apc lut en = 0) memory type volatile 85h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for apc and recalled from a2h table 06h in the apc and dual-closed-loop mode at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. factory default 0000h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access (pw2 and apc lut en = 0) or (pw1 and rwtbl246 and apc lut en = 0) memory type volatile 86h 0 0 0 0 0 0 2 9 2 8 87h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for bias and recalled from a2h table 06h in the open-loop mode at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. factory default ffh read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 88h 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 dacfs sets the slope of the dac?s temperature compensation. in conjunction with dac offset and tindex, this allows the dac to create an output that is linearly dependent on temperature. for further details see the delta- sigma output and reference section. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 64 maxim integrated a2h table 02h, register 89h: cnfga factory default 82h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 89h losc reserved inv los reserved mask reserved burst_mode invtxfi bit 7 bit 0 bit 7 losc: enables losout due to input pin los. 0 = losout is affected by the los input.1 = losout is not affected by changed in the los input. bit 6 reserved bit 5 inv los: inverts the buffered input pin los to output pin losout. 0 = noninverted los to losout pin.1 = inverted los to losout pin. bit 4 reserved bit 3 mask:0 = alarm enable row exists at a2h table 01h, registers f8h?ffh. a2h table 05h, registers f8h? ffh are empty. 1 = alarm enable row exists at a2h table 05h, registers f8h?ffh. a2h table 01h, registers f8h? ffh are empty. bit 2 reserved bit 1 burst_mode:0 = txp is derived from the txmon input. 1 = txp is calculated from md0 and md1, which are read from the max3710 through the 3-wire interface. bit 0 invtxfi: allow for inversion of signal driven by txf input pin. 0 = (default) txf signal is not inverted.1 = txf signal is inverted. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 65 maxim integrated a2h table 02h, register 8ah: cnfgb factory default 40h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 8ah reserved biasmod_rsten reserved reserved reserved alatch reserved wlatch bit 7 bit 0 bit 7 reserved bit 6 biasmod_rsten: 0 = biasreg and modreg when set to 0 do not cause a restart.1 = (default) when biasreg = 0 or modreg = 0 in the max3710, the txctrl6 restart and soft_ restart bits are set to 1. bits 5:3 reserved bit 2 alatch: adc alarm?s comparison latch. a2h table 01h, registers 70h?71h. 0 = adc alarm and flags reflect the status of the last comparison.1 = adc alarm flags remain set. bit 1 reserved bit 0 wlatch: adc warning?s comparison latch. a2h table 01h, registers 74h?75h. 0 = adc warning flags reflect the status of the last comparison.1 = adc warning flags remain set. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 66 maxim integrated a2h table 02h, register 8bh: cnfgca2h table 02h, register 8ch: reserved factory default 10h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 8bh xoveren reserved txdm3 biasmodovfl_flt txdflt txdio rssi_fc rssi_ff bit 7 bit 0 bit 7 xoveren: enables rssi conversion to use the xover (a2h table 02h, register 90h?91h) value during rssi conversions.0 = uses hysteresis for linear rssi measurements. 1 = xover value is enabled for nonlinear rssi measurements. bit 6 reserved bit 5 txdm3: enables txd to reset alarms and warnings associated to rssi during a txd event. 0 = txd event has no affect on the rssi alarms and warnings.1 = rssi alarms and warnings are reset during a txd event. bit 4 biasmodovfl_flt:0 = ibiasovfl and imodovfl bits in the dpcstat register in the max3710 have no affect on txfout. 1 = ibiasovfl or imodovfl bits when set to 1 in the dpcstat register in the max3710 cause the txfout pin to be set to 1. bit 3 txdflt: see figure 10. 0 = txf pin has no affect on txdout.1 = txf pin is enabled and ored with other possible signals to create txdout. bit 2 txdio: see figure 10. 0 = (default) txd input signal is enabled and ored with other possible signals to create txdout.1 = txd input signal has no affect on txdout. bits 1:0 rssi_fc and rssi_ff: rssi force coarse and rssi force fine. control bits for rssi mode of operation on the rssi conversion.00b = (default) normal rssi mode of operation. 01b = the fine settings of scale and offset are used for rssi conversions. 10b = the coarse settings of scale and offset are used for rssi conversions. 11b = normal rssi mode of operation. power-on value 00h read access n/a write access n/a memory type this register is reserved. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 67 maxim integrated a2h table 02h, register 8dh: cnfgda2h table 02h, register 8eh: right-shift 1 (rshift 1 ) factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 8dh inv_dac reserved reserved reserved ds1863_mode pow_lev_ds1863 bit 7 bit 0 bit 7 inv_dac:0 = dac output is inverted. 1 = dac output is not inverted. bits 6:4 reserved bit 3 ds1863_mode:0 = normal operation. power leveling defined in a2h lower memory, register 6fh. 1 = ds1863 mode. this mode is usually used for systems upgrading from the ds1863. in this mode, krmd[2:0] in the max3710 is directly written to by the pow_lev_ds1863 bits. bits 2:0 pow_lev_ds1863[2:0] power level (db) 000 0 001 0 010 0 011 -3 100 -3 101 -3 110 -6 111 -6 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 8eh reserved txb 2 txb 1 txb 0 reserved txp 2 txp 1 txp 0 bit 7 bit 0 allows for right-shifting the final answer of txb and txp voltage measurements. this allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 68 maxim integrated a2h table 02h, register 8fh: right-shift 0 (rshift 0 ) a2h table 02h, register 90h?91h: xover coarse factory default 30h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 8fh reserved rssif 2 rssif 1 rssif 0 reserved rssic 2 rssic 1 rssic 0 bit 7 bit 0 allows for right-shifting the final answer of rssi fine and coarse voltage measurements. this allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. factory default 0000h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) 90h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 91h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 0 bit 7 bit 0 defines the crossover value for rssi measurements of nonlinear inputs when xoveren is set to a 1 (a2h table 02h, register 8bh). rssi coarse conversion results (before right-shifting) less than this register are clamped to the value of this register. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 69 maxim integrated a2h table 02h, register 92h?93h: v cc scale a2h table 02h, register 94h?95h: txb scalea2h table 02h, register 96h?97h: txp scale a2h table 02h, register 98h?99h: rssi fine scale a2h table 02h, register 9ah?9bh: reserved a2h table 02h, register 9ch?9dh: rssi coarse scale a2h table 02h, register 9eh?9fh: reserved factory calibrated read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 92h, 94h, 96h, 98h, 9ch 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 93h, 95h, 97h, 99h, 9dh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 controls the scaling or gain of the full-scale voltage measurements. the factory-calibrated value produces a full-scale voltage of 6.5536v for v cc ; 2.5v for txb, txp, and mon4; and 0.3125v for rssi fine. factory default 00h read access n/a write access n/a memory type nonvolatile (see) these registers are reserved. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 70 maxim integrated a2h table 02h, register a0h?a1h: xover finea2h table 02h, register a2h?a3h: v cc offset a2h table 02h, register a4h?a5h: txb offseta2h table 02h, register a6h?a7h: txp offset a2h table 02h, register a8h?a9h: rssi fine offset a2h table 02h, register aah?abh: reserved a2h table 02h, register ach?adh: rssi coarse offset factory default ffffh read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) a0h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 a1h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 0 bit 7 bit 0 defines the crossover value for rssi measurements of nonlinear inputs when xoveren is set to 1 (a2h table 02h, register 8bh). rssi fine conversion results (before right-shifting) greater than this register require a rssi coarse conversion. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) a2h, a4h, a6h, a8h, ach s 2 15 2 14 2 13 2 12 2 11 2 10 2 9 a3h, a5h, a7h, a9h, adh 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 bit 7 bit 0 allows for offset control of these voltage measurements if desired. this number is two?s complement. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 71 maxim integrated a2h table 02h, register aeh?afh: internal temp offseta2h table 02h, register b0h?b3h: pw1 factory calibrated read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) aeh s 2 8 2 7 2 6 2 5 2 4 2 3 2 2 afh 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 bit 7 bit 0 allows for offset control of temp measurement if desired. the final result must be xored with bb40h before writing to this register. factory calibration contains the desired value for a reading in degrees celsius. factory default ffff ffffh read access n/a write access pw2 or (pw1 and wpw1) memory type nonvolatile (see) b0h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 b1h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b2h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 b3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the pwe value is compared against the value written to this location to enable pw1 access. at power-on, the pwe value is set to all ones. thus, writing these bytes to all ones grants pw1 access on power-on without writing the password entry. all reads of this register are 00h. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 72 maxim integrated a2h table 02h, register b4h?b7h: pw2a2h table 02h, register b8h?bfh: empty factory default ffff ffffh read access n/a write access pw2 memory type nonvolatile (see) b4h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 b5h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b6h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 b7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the pwe value is compared against the value written to this location to enable pw2 access. at power-on, the pwe value is set to all ones. thus, writing these bytes to all ones grants pw2 access on power-on without writing the password entry. all reads of this register are 00h. factory defaultread access n/a write access n/a memory type these registers are empty. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 73 maxim integrated a2h table 02h, register c0h: pw_ena factory default 10h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) c0h rwtbl89 rwtbl1c rwtbl2 rwtbl1a rwtbl1b wa2 lower wauxa wauxb bit 7 bit 0 bit 7 rwtbl89: tables 08h?09h. 0 = (default) read and write access for pw2 only.1 = read and write access for both pw1 and pw2. bit 6 rwtbl1c: a2h table 01h or 05h bytes f8?ffh. table address is dependent on mask bit (a2h table 02h, register 89h).0 = (default) read and write access for pw2 only. 1 = read and write access for both pw1 and pw2. bit 5 rwtbl2: table 02h except for pw1 value locations (a2h table 02h, registers b0h?b3h). 0 = (default) read and write access for pw2 only.1 = read and write access for both pw1 and pw2. bit 4 rwtbl1a: read and write a2h table 01h, registers 80h?bfh. 0 = read and write access for pw2 only.1 = (default) read and write access for both pw1 and pw2. bit 3 rwtbl1b: read and write a2h table 01h, registers c0h?f7h. 0 = (default) read and write access for pw2 only.1 = read and write access for both pw1 and pw2. bit 2 wa2 lower: write lower memory bytes 00h?5fh in main memory. all users can read this area. 0 = (default) write access for pw2 only.1 = write access for both pw1 and pw2. bit 1 wauxa: write auxiliary memory, registers 00h?7fh. all users can read this area (see also a2h table 02h, register c1h, pw_enb).0 = (default) write access for pw2 only. 1 = write access for both pw1 and pw2. bit 0 wauxb: write auxiliary memory, registers 80h?ffh. all users can read this area (see also a2h table 02h, register c1h, pw_enb).0 = (default) write access for pw2 only. 1 = write access for both pw1 and pw2. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 74 maxim integrated a2h table 02h, register c1h: pw_enb factory default 03h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) c1h rwtbl46 rtbl1c rtbl2 rtbl1a rtbl1b wpw1 wauxau wauxbu bit 7 bit 0 bit 7 rwtbl46: read and write tables 04h and 06h. 0 = (default) read and write access for pw2 only.1 = read and write access for both pw1 and pw2. bit 6 rtbl1c: read a2h table 01h or a2h table 05h, registers f8h?ffh. table address is dependent on the mask bit (a2h table 02h, register 89h).0 = (default) read access for pw2 only. 1 = read access for both pw1 and pw2. bit 5 rtbl2: read a2h table 02h except for pw1 value locations (a2h table 02h, registers b0h?b3h). 0 = (default) read access for pw2 only.1 = read access for both pw1 and pw2. bit 4 rtbl1a: read a2h table 01h, registers 80h?bfh. 0 = (default) read access for pw2 only.1 = read access for both pw1 and pw2. bit 3 rtbl1b: read a2h table 01h, registers c0h-f7h. 0 = (default) read access for pw2 only.1 = read access for both pw1 and pw2. bit 2 wpw1: write register pw1 (a2h table 02h, registers b0h?b3h). for security purposes these registers are not readable.0 = (default) write access for pw2 only. 1 = write access for both pw1 and pw2. bit 1 wauxau: write auxiliary memory, registers 00h?7fh. all users can read this area (see also a2h table 02h, register c0h, pw_ena).0 = write access for pw2 only. 1 = (default) write access for user, pw1, and pw2. bit 0 wauxbu: write auxiliary memory, registers 80h?ffh. all users can read this area (see also a2h table 02h, register c0h, pw_ena)0 = write access for pw2 only. 1 = (default) write access for user, pw1, and pw2. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 75 maxim integrated a2h table 02h, register c2h?c6h: reserveda2h table 02h, register c7h: tblselpon a2h table 02h, register c8h?c9h: dac value factory default 00h read access n/a write access n/a memory type nonvolatile (see) these registers are reserved. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) c7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 chooses the initial value for the tbl sel byte (lower memory, register 7fh) at power-on. factory default 0000h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access (pw2 and bias lut en = 0) or (pw1 and rwtbl246 and bias lut en = 0) memory type volatile c8h 0 0 0 0 0 0 2 9 2 8 c9h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 value written to dac when dac_en = 0, or calculated using the formula stated in the delta-sigma output and reference section. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 76 maxim integrated a2h table 02h, register cah: incbytea2h table 02h, register cbh: txctrl5 dpc a2h table 02h, register cch: imodmax factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access (pw2 and bias lut en = 0) or (pw1 and rwtbl246 and bias lut en = 0) memory type volatile cah 2 3 2 2 2 1 2 0 2 3 2 2 2 1 2 0 bit 7 bit 0 7:4: value written to max3710 biasinc[3:0] from lut. this must be set to 0 in open-loop mode.3:0: value written to max3710 modinc[3:0] from lut. this must be set to 0 in open-loop mode and apc mode. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access (pw2 and apc lut en = 0) or (pw1 and rwtbl246 and apc lut en = 0) memory type volatile cbh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 value written to max3710 txctrl5 from the txctrl5 lut. the txctrl5 lut is only active during the dual closed loop mode. for open loop and apc loop mode, see register e8h. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type volatile cch 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 bit 7 bit 0 value written to max3710 imodmax from the mod max lut. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 77 maxim integrated a2h table 02h, register cdh: ibiasmaxa2h table 02h, register ceh: device id a2h table 02h, register cfh: device ver factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type volatile cdh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 value written to max3710 ibiasmax from the bias max lut. factory default 86h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access n/a memory type rom ceh 1 0 0 0 0 1 0 0 bit 7 bit 0 hardwired connections to show the device id. factory default device version read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access n/a memory type rom cfh device version bit 7 bit 0 hardwired connections to show the device version. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 78 maxim integrated a2h table 02h, register d0h?dfh: emptya2h table 02h, register e0h: rxctrl1 a2h table 02h, register e1h: rxctrl2 factory default 00h read access n/a write access n/a memory type none these registers do not exist. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) e0h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), a maxim laser driver tx_por bit is set high (visible in 3-wire txstat1 bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) e1h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), a maxim laser driver tx_por bit is set high (visible in 3-wire txstat1 bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 79 maxim integrated a2h table 02h, register e2h: setcmla2h table 02h, register e3h: setlosh a2h table 02h, register e4h: txctrl1 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) e2h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), a maxim laser driver tx_por bit is set high (visible in 3-wire txstat1 bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) e3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. only written if setlosctl is 1. if setlosctl is 0, then setlosl register is used. after either v cc exceeds poa (after a por event), a maxim laser driver tx_por bit is set high (visible in 3-wire txstat1 bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) e4h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), a maxim laser driver tx_por bit is set high (visible in 3-wire txstat1 bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 80 maxim integrated a2h table 02h, register e5h: txctrl2a2h table 02h, register e6h: txctrl3 a2h table 02h, register e7h: txctrl4 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) e5h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), a maxim laser driver tx_por bit is set high (visible in 3-wire txstat1 bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) e6h 2 7 2 6 2 5 2 4 2 3 pow_lev_init 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), a maxim laser driver tx_por bit is set high (visible in 3-wire txstat1 bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. for bits 2:1, see the pow_lev[1:0] bits in a2h lower memory, register 6fh and table 11a and table 11b . factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) e7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), a maxim laser driver tx_por bit is set high (visible in 3-wire txstat1 bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 81 maxim integrated a2h table 02h, register e8h: txctrl5 apc ola2h table 02h, register e9h: txctrl6 a2h table 02h, register eah: txctrl7 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) e8h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), a maxim laser driver tx_por bit is set high (visible in 3-wire txstat1 bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. this register is active only during the open loop and apc loop modes. see register cbh for txctrl5 access during the dual closed-loop mode. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) e9h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), a maxim laser driver tx_por bit is set high (visible in 3-wire txstat1 bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) eah 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), a maxim laser driver tx_por bit is set high (visible in 3-wire txstat1 bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 82 maxim integrated a2h table 02h, register ebh: reserveda2h table 02h, register ech: setlosh_3945 a2h table 02h, register edh: setlosl_3945 factory default 00h read access n/a write access n/a memory type nonvolatile (see) this register is reserved. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) ech 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) edh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. only written if setlosctl is 0. if setlosctl is 1, then the setlosh register is used. after either v cc exceeds poa (after a por event), a maxim laser driver tx_por bit is set high (visible in 3-wire txstat1 bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 83 maxim integrated a2h table 02h, register eeh: setlostimer_3945a2h table 02h, register efh: 3wset factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) eeh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), a maxim laser driver tx_por bit is set high (visible in 3-wire txstat1 bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. factory default 60h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) efh temp_upd en_3945 rstrt_3710 reserved reserved reserved reserved reserved bit 7 bit 0 bit 7 temp_upd: 0 = default 3-wire operation.1 = all the control registers (from register 0eh?e8h and register eah) are written every temperature conversion. bit 6 en_3945:0 = bytes associated with the max3945 are not sent on the 3-wire bus. 1 = bytes associated with the max3945 are transmitted on the 3-wire bus on power-up (after v cc crosses the vcc lo alarm). bit 5 rstrt_3710:0 = txinlos (txstat1 register) does not affect system restart. 1 = when txinlos (txstat1 register) is set, register e9h (txctrl6) is written to max3710 periodically every t rr . bits 4:0 reserved downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 84 maxim integrated a2h table 02h, register f0h: 3wctrla2h table 02h, register f1h: address factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type volatile f0h reserved reserved reserved reserved reserved 3wman_3945 3wrw 3wdis bit 7 bit 0 bits 7:3 reserved bit 2 3wman_3945: when this bit is set when 3wrw is set, only the max3945 is written using cselout2. bit 1 3wrw: initiates a 3-wire read or write operation. the write command uses the memory address found in the 3-wire address register (a2h table 02h, register f1h) and the data from the 3-wire write register (a2h table 02h, register f2h). the read command uses the memory address found in the 3-wire address register (a2h table 02h, register f1h). the address determines whether a read or write operation is to be performed. this bit clears itself at the completion of the operation. 0 = (default) reads back as 0 when the read or write operation is completed. 1 = initiates a 3-wire read or write operation. bit 0 3wdis: disables all automatic communication across the 3-wire interface. this includes all updates from the luts, the apc loop, and status registers updates. the only 3-wire communication is with the manual mode of operation. 0 = (default) automatic communication is enabled. 1 = disables automatic communication. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) f1h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 this byte is used during manual 3-wire communication. when a manual read or write is initiated, this register contains the address for the operation. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 85 maxim integrated a2h table 02h, register f2h: writea2h table 02h, register f3h: read a2h table 02h, register f4h: txstat2 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) f2h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 this byte is used during manual 3-wire communication. when a manual write is initiated, this register contains the address for the operation. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access n/a memory type volatile f3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 this byte is used during maunual 3-wire communication. when a manual read is initiated, the return data is stored in this register. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access n/a memory type nonvolatile (see) f4h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. this value is read from a maxim laser driver with the 3-wire interface every t rr (see the analog voltage monitoring characteristics table). downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 86 maxim integrated a2h table 02h, register f5h: txstat1a2h table 02h, register f6h: dpcstat a2h table 02h, register f7h: rxstat a2h table 02h, register f8h?ffh: reserved factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access n/a memory type nonvolatile (see) f5h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. this value is read from a maxim laser driver with the 3-wire interface every t rr (see the analog voltage monitoring characteristics table). factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access n/a memory type nonvolatile (see) f6h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. this value is read from a maxim laser driver with the 3-wire interface every t rr (see the analog voltage monitoring characteristics table). factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access n/a memory type nonvolatile (see) f7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. this value is read from a maxim laser driver with the 3-wire interface every t rr (see the analog voltage monitoring characteristics table). factory default 00h read access n/a write access n/a memory type nonvolatile (see) these registers are reserved. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 87 maxim integrated a2h table 04h register descriptions a2h table 04h, register 80h?a7h: modulation or txctrl5 luta2h table 04h, register f0h?f7h: mod max lut a2h table 04h, register a8h?efh: empty factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (ee) f0h?f7h 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 bit 7 bit 0 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (ee) open loop and apc loop (modulation), dual closed loop (txctrl5) 80h?a7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 the digital value for the modulation dac output or txctrl5 register in max3710. the modulation lut is a set of registers assigned to hold the temperature profile for the modulation register. the temperature measurement is used to index the lut (tindex, a2h table 02h, register 81h) in 2 n c increments from -40 n c to +102 n c, starting at 80h. values recalled from this eeprom memory table are written into the modulation value register (a2h table 02h, register 82h?83h) location, which holds the value until the next temperature conversion. the part can be placed into a manual mode (mod lut en bit, a2h table 02h, register 80h), where modulation register is directly controlled for calibration. if the temperature compensation functionality is not required, then program the entire table to the desired modulation setting. see the bias, modulation, set_2xapc, txctrl5 luts section for more details. the modulation value written to the register is determined as follows: modulation value = modulation lut + 4 x mod offset lut factory defaultread access n/a write access n/a memory type these registers are empty. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 88 maxim integrated a2h table 04h, register f8h?ffh: mod offset or set_imod lut a2h table 06h register descriptions a2h table 06h, register 80h?a7h: bias or set_ibias factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (ee) open loop, apc loop, and dual closed loop (set_imod) f8h?ffh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (ee) open loop 80h?a7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 apc loop and dual closed loop 80h?a7h 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 the bias lut is a set of registers assigned to hold the temperature profile for the bias reference dac. the temperature measurement is used to index the lut (tindex, a2h table 02h, register 81h) in 2 n c increments. values recalled from this eeprom memory table are written into the bias or set_ibias location, which holds the value until the next temperature conversion. the part can be placed into a manual mode, where bias or set_ibias can be directly controlled for calibration. if te temperature compensation is not required by the application, program the entire lut to the desired bias value. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 89 maxim integrated a2h table 06h, register f0h?f7h: bias max luta2h table 06h, register f8h?ffh: bias offset or apc lut a2h table 06h, register a8h?efh: empty factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (ee) f0h?f7h 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (ee) open loop f8h?ffh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 apc loop and dual closed loop (apc) f8h?ffh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 factory defaultread access n/a write access n/a memory type these registers are empty. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 90 maxim integrated a2h table 08h register descriptions a2h table 08h, register 80h?f7h: emptya2h table 08h, register f8h?ffh: incbyte a2h table 09h register descriptions a2h table 09h, register 80h?f7h: emptya2h table 09h, register f8h?ffh: dac offset lut factory default 00h read access pw2 or (pw1 and rwtbl78) or (pw1 and rtbl78) write access pw2 or (pw1 and rwtbl78) memory type nonvolatile (ee) f8h?ffh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 bits 7:4 update the upper nibble of the incbyte register (table 02h, register cah). bits 3:0 update the lower nibble of the incbyte register. see the incbyte register descriptions for more details. factory defaultread access n/a write access n/a memory type these registers are empty. factory default 00h read access pw2 or (pw1 and rwtbl78) or (pw1 and rtbl78) write access pw2 or (pw1 and rwtbl78) memory type nonvolatile (ee) f8h?ffh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 factory defaultread access n/a write access n/a memory type these registers are empty. downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface 91 maxim integrated auxiliary memory a0h register description auxiliary memory a0h, register 00h?ffh: eeprom applications information power-supply decoupling to achieve best results, it is recommended that the power supply is decoupled with a 0.01f or a 0.1f capacitor. use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the v cc and gnd pins to minimize lead inductance. layout considerations connect all gnd pins to a common ground plane. connect all v cc pins together. sda and scl pullup resistors sda is an open-collector output on the device that requires a pullup resistor to realize high-logic levels. a master using either an open-collector output with a pul - lup resistor or a push-pull output driver can be used for scl. pullup resistor values should be chosen to ensure that the rise and fall times listed in the i 2 c ac electrical characteristics are within specification. ordering information + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel.* ep = exposed pad. package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. factory default 00h read access pw2 or (pw1 and rwauxa) or (pw1 and rwauxau) write access pw2 or (pw1 and rwauxa) memory type nonvolatile (ee) 00h?ffh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 accessible with the slave address a0h. part temp range pin-package DS1886T+ -40 n c to +95 n c 24 tqfn-ep* DS1886T+t -40 n c to +95 n c 24 tqfn-ep* package type package code outline no. land pattern no. 24 tqfn-ep t2445+1 21-0201 90-0083 downloaded from: http:///
ds1886 sfp and pon onu controller with digital ldd interface maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 92 ? 2012 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 3/12 initial release ? 1 8/12 made numerous lut addressing changes for txinlos 30, 32, 33, 39, 83, 87, 88, 89 downloaded from: http:///

▲Up To Search▲

Price & Availability of DS1886T

	To Download DS1886T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .